In GICv2, per-core interrupts (SGIs and PPIs) are configured through banked registers in the distributor, which means that a core cannot access the configuration of the SGIs and PPIs of the other cores.
By contrast, GICv3 moves this configuration to redistributors, which are apparently mapped at pairwise distinct addresses, and it seems that every distributor can be accessed by every core (although the spec is unclear on this point). For instance, on some operating systems, a core will scan regions of redistributors in memory, using GICR_TYPER.Affinity_Value to match them to cores, and GICR_TYPER.Last to discover where a region ends.
Does it mean that an implementation is required to allow every core to configure the SGIs and PPIs of every other core?
Essentially - yes. But I would describe it differently. In GICv2, the GIC needed to know who was accessing it in order to select the correct banked copy of a register. In GICv3 (non-legacy mode) it's simpler, the GIC doesn't need to care where the access came from as it doesn't change what register is accessed.
Thank you for your answer. Whether GICv3 is simpler than GICv2 in that respect is debatable. For some implementations--e.g. for a hypervisor--GICv3 forces the data structures tracking the states of virtual SGIs and PPIs to be shared between CPUs, whilst they could almost be kept private in GICv2. But I concede that GICv3 makes handling virtual SGIs, PPIs and SPIs more uniform.