Hello I am new to AXI and just saw the pseudocode for a transfer in the spec of AXI . My question is regarding Data_Bus_Bytes .
Q1- The spec says that Data_Bus_Bytes is number of 8 bit byte lanes in the bus. Is it same as Number_Bytes which is 2^AWSIZE ?
Q2 - where are we going to use Upper byte lane and lower byte lane further?
Hi Rana,
Q1. No.
"Data_Bus_Bytes" indicates the physical width of the available data bus, whereas AWSIZE indicates the width of the specific transaction the master is performing. So you could have a 64-bit data bus (Number_Data_Bytes=8) and the master is performing 32-bit transfers (AWSIZE=3'b010).
Q2. I must admit that I've never liked all of these pseudocode descriptions (defined in A3.4.1 and used in examples in A3.4.2), I'm not sure they really help (perhaps that's just me).
I guess the upper and lower byte lane calculations are there to help someone better understand the range of byte lanes that can be used for each transfer in a transaction.
But rather than use these equations I find it easier to just work out the address for each transfer in the transaction (so taking into account the start address, the burst type indicating how to modify the address for each transfer after the first, and AxSIZE indicating by how much to change the address for each transfer), and then once you know the address for the transfer (that's the difficult part), the range of byte lanes used is then simply the AxSIZE width above this address.
I suppose that IS what the pseudocode descriptions/calculations are demonstrating for people who prefer calculations, but I prefer words.