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burst-based transactions on AXI

PJ_

Hi,

I'm confusing with burst transaction in AXI.


there is one key feature in AXI spec....
> "burst-based transactions with only start address issued"

How can we understand this point?

Thanks,

  • 0

    In the AHB protocol every transfer comes with an address value on HADDR. As you already know how the address will change because of what is signalled on HBURST, HTRANS and HSIZE, the HADDR information for all transfers after the start of the burst could be considered unnecessary as the target slave could calculate the addresses for transfers after the start of the burst.

    In AXI the aim was to reduce unnecessary bus traffic, so here the master just issues the address for the start of a burst, and that is all that is required on the address channel. The target slave then calculates the address changes for each subsequent transfer in the burst based on what it sampled on AxADDR, AxSIZE, AxBURST and AxLEN.

    So for example, if the AXI master signals an INCR burst of 4 transfers, with AxSIZE signalling 32-bit transfers, and AxADDR is 0x4, the slave can then see that the transfers for this burst will be to 0x4, 0x8, 0xC and 0x10.