AXI4 - read data interleaving

Hi Xingguang,

Thanks for the reply but I still have some concern on last line of your reply.

Let me get a reconfirmation on mixing of two bursts.

There are two two read transactions issued by Master X and Y, each with 4 beat of single burst.

I agree to your point of X and Y can start in any order, but what I thought is that

Once and of the transaction start, it will complete before other transaction can begin. As both the transactions are of single burst.

It can be

Seq 1: X1 X2 X3 X4 Y1 Y2 Y3 Y4

or

Seq 2: Y1 Y2 Y3 Y4 X1 X2 X3 X4

but not

Seq 3: X1 Y1 X2 Y2 X3 X4 Y3 Y4

Where X1 and Y1 represents one beat of a single burst.

If you are suggesting that data can come in Seq 3, can you please point me to a reference for that.

Thanks,

Amit

Hi Xingguang,

Thanks for the reply but I still have some concern on last line of your reply.

Let me get a reconfirmation on mixing of two bursts.

There are two two read transactions issued by Master X and Y, each with 4 beat of single burst.

I agree to your point of X and Y can start in any order, but what I thought is that

Once and of the transaction start, it will complete before other transaction can begin. As both the transactions are of single burst.

It can be

Seq 1: X1 X2 X3 X4 Y1 Y2 Y3 Y4

or

Seq 2: Y1 Y2 Y3 Y4 X1 X2 X3 X4

but not

Seq 3: X1 Y1 X2 Y2 X3 X4 Y3 Y4

Where X1 and Y1 represents one beat of a single burst.

If you are suggesting that data can come in Seq 3, can you please point me to a reference for that.

Thanks,

Amit

Hello Amit,

>Seq 1: X1 X2 X3 X4 Y1 Y2 Y3 Y4

>or

>Seq 2: Y1 Y2 Y3 Y4 X1 X2 X3 X4

>but not

>Seq 3: X1 Y1 X2 Y2 X3 X4 Y3 Y4

>Where X1 and Y1 represents one beat of a single burst.

>If you are suggesting that data can come in Seq 3, can you please point me to a reference for that.

Seq 3 is possible.

Confirmation can be found in the AXI/ACE specification (ARM IHI 0022E):

Section A5.3.1

===============================================================

Data from read transactions with different ARID values can arrive in any order. Read

data of transactions with different ARID values can be interleaved.

===============================================================

Regards,

Xingguang

Hello Amit,

<<ARM IHI 0022E>> is available at:

ARM Information Center

  --> AMBA

      --> AMBA specifications

           --> AMBA AXI and ACE specification

               --> Issue E

You may need to register as an ARM user before downloading.

H Xingguang,

Thanks for the reference, but I have already gone through that earlier. Though it does say that data can arrive in any order but it does not clarify if it can be mixed in a single burst.

Earlier I have serched the web to find a reference. I dint find anything to confirm my claim of Data interleaving from two data burst is not possible however, I did find it for write transaction (not for read which I was looking for).

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0363g/Chdfahii.html

• The AXI master does not interleave write data from two different bursts, even if the bursts have different IDs.

I thought same should be applicable for read also, until unless it documented somewhere, that data interleaving for different burst in read transaction is allowed.

Thanks,

Amit

As you will be knowing, Write data interleaving support is discontinued from AXI-4, The link is just for reference.

Thanks,

Amit

Hi Amit,

Hopefully the picture below can illustrate the permitted read data behavior.

There are two AR transactions with different IDs. The RDATA in this example is both out of order and interleaved. It is just a mixture of the following two statements from the spec:

==========================================================

Data from read transactions with different ARID values can arrive in any order.

Read data of transactions with different ARID values can be interleaved.

==========================================================

Regarding write data interleaving, the requirements are different from those for read data.

AXI3: Write data interleaving (for different IDs) is supported. But the first item of write data must be issued in the same order as the write address.

AXI4: Write data interleaving is not supported.

Although write data interleaving is allowed in AXI3, masters developed by ARM (such as Cortex-R4) do not generate interleaved write data.

Regards,

Xingguang

Hi Xingguang,

Thanks for all your time and effort. I don't find anything wrong in accepting your views and most likely you are correct. But I think it should be gratified, different people understand things differently. Its just two different way of looking at same thing. As you are and Employee, I would take your views but please ask someone to document it. Again thanks a lot.

Thanks,'Amit