How are the PCIe lanes of the JUNO system connected

Hi martinlangner,

These are supplements to Ash Wilding's answer.

From Table 2-5 of Juno (both r1 and r2) ARM Development Platform Technical Reference Manual:

     Slot number     Connector size-PCIe lanes     Used lanes     Unused lanes

     Slot 0                ×4                         1                3

     Slot 1                ×4                         1                3

     Slot 2                ×8                         4                4

     Slot 3               ×16                         4               12

If you are more familiar with the notation for PCIe lanes:

     Slot 0 is  ×4 (×1 mode) or Slot 0 is  ×4 @ ×1

     Slot 1 is  ×4 (×1 mode) or Slot 1 is  ×4 @ ×1

     Slot 2 is  ×8 (×4 mode) or Slot 2 is  ×8 @ ×4

     Slot 3 is ×16 (×4 mode) or Slot 3 is ×16 @ ×4

Does every connector have 4 independent lanes (so all together we could use 4 cards with 4 lanes each at the same time)

or are the 4 lanes shared so when we are using 4 cards only one lane is available per card?

PCIe uses point-to-point topology, separate link (1 or more lane/s) for every endpoint. PCIe endpoints connect to the root complex using separate links, or multiple endpoints can use a common link to the root complex through a switch. From Figure 2-1 (Juno r1 and r2 TRM), Figure 2-16 (Juno r1 TRM), and Figure 2-17 (Juno r2 TRM), the 4-lane link to the root complex is shared by the four slots (also by the SATA 2.0 controller and Gigabit Ethernet controller) using a PCIe switch.

No lane is DIRECTLY SHARED (DIRECTLY SHARED = direct connection, as if the lane/s is/are common physical bus) by two or more endpoints. The available lanes for the slots can be found in the Used lanes column of Table 2-5; 1 lane for Slot 0, 1 lane for Slot 1, 4 lanes for Slot 2, and 4 lanes for Slot 3.

Regards,

Goodwin

Hi martinlangner,

These are supplements to Ash Wilding's answer.

From Table 2-5 of Juno (both r1 and r2) ARM Development Platform Technical Reference Manual:

     Slot number     Connector size-PCIe lanes     Used lanes     Unused lanes

     Slot 0                ×4                         1                3

     Slot 1                ×4                         1                3

     Slot 2                ×8                         4                4

     Slot 3               ×16                         4               12

If you are more familiar with the notation for PCIe lanes:

     Slot 0 is  ×4 (×1 mode) or Slot 0 is  ×4 @ ×1

     Slot 1 is  ×4 (×1 mode) or Slot 1 is  ×4 @ ×1

     Slot 2 is  ×8 (×4 mode) or Slot 2 is  ×8 @ ×4

     Slot 3 is ×16 (×4 mode) or Slot 3 is ×16 @ ×4

Does every connector have 4 independent lanes (so all together we could use 4 cards with 4 lanes each at the same time)

or are the 4 lanes shared so when we are using 4 cards only one lane is available per card?

PCIe uses point-to-point topology, separate link (1 or more lane/s) for every endpoint. PCIe endpoints connect to the root complex using separate links, or multiple endpoints can use a common link to the root complex through a switch. From Figure 2-1 (Juno r1 and r2 TRM), Figure 2-16 (Juno r1 TRM), and Figure 2-17 (Juno r2 TRM), the 4-lane link to the root complex is shared by the four slots (also by the SATA 2.0 controller and Gigabit Ethernet controller) using a PCIe switch.

No lane is DIRECTLY SHARED (DIRECTLY SHARED = direct connection, as if the lane/s is/are common physical bus) by two or more endpoints. The available lanes for the slots can be found in the Used lanes column of Table 2-5; 1 lane for Slot 0, 1 lane for Slot 1, 4 lanes for Slot 2, and 4 lanes for Slot 3.

Regards,

Goodwin