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Random behavior with SCTLR_EL1 reset values

Hi,

I am working on Juno and I am using SCTLR_EL1 reset value based on A53 spec is = 0x00C50838

but If I look to ARMv8 spec it shows some reserved bits as 1 and considering that reset values = 0x30D50800.

I am seeing some MMU random behavior at EL1 based on reset value as the same code sometimes gives stage 1 fault and other times stage 2 fault.

Please let me know what should be the correct SCTLR_EL1 reset value ?

Thanks.

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  • I must admit that I'd hadn't checked the reset value before, as the architecture describes the register as:

    Some or all RW fields of this register have defined reset values. These apply only if the PE resets

    into EL1 using AArch64. Otherwise, RW fields in this register reset to IMPLEMENTATION DEFINED

    values that might be UNKNOWN.

    I would suggest working on the assumption that the register is UNKNOWN at reset, as that is more portable.

    That aside.... When are you reading SCTLR_EL1?  One answer would be that something earlier in the boot flow wrote to it already.

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  • I must admit that I'd hadn't checked the reset value before, as the architecture describes the register as:

    Some or all RW fields of this register have defined reset values. These apply only if the PE resets

    into EL1 using AArch64. Otherwise, RW fields in this register reset to IMPLEMENTATION DEFINED

    values that might be UNKNOWN.

    I would suggest working on the assumption that the register is UNKNOWN at reset, as that is more portable.

    That aside.... When are you reading SCTLR_EL1?  One answer would be that something earlier in the boot flow wrote to it already.

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