I am now writing a hyper-visor based on arm-v8 aarch64. and now Linux kernel can boot successfully on this hyper-visor. and I test the code on DS5. But there is a cache issue.
The issue is:
after Linux kernel modify the content of translation table (such as called io_remap to map some device memory), it need to flush the related cache, otherwise when accessing the memory space which mapped by io_remap will cause an EL1 data abort.
I found in the DS5 cache view, when executed in EL1， only the content of translation table are cached, but other EL1 memory are not. so question is:
1: what the EL1 cache state when EL2 is implemented?
2: why it is need do cache flush after change the translation table ? what am I missing ?
the issue seems that CPU think the cache is disabled in EL1, but the translation table content is cached, so when do translation walk, cpu will not fetch content from the cache.
Thanks
Depending on the required synchronization, a program might use memory barriers on their own, or it might use themin conjunction with cache maintenance and memory management instructions that in general are only availablewhen software execution is at EL1 or higher.
Execution of DSB at EL2 ensures that any memory accesses caused by speculative translation table walks from the Non-secure EL1&0 translation regime have been observed.