Hi,
I am trying to cross compile "EB_TrustZone_Example" using "arm-none-eabi-gcc"
Modified "#__smc(0) void yeild(void);" with "__asm__(" smc #0");" in main_normal.c
I have followed the following steps to compile.
arm-none-eabi-gcc -c --debug -mcpu=cortex-a5 -O1 -o ./obj/main_normal.o ./src/main_normal.c
arm-none-eabi-gcc -c --debug -mcpu=cortex-a5 -O1 -o ./obj/retarget_normal.o ./src/retarget_normal.c
arm-none-eabi-as -mcpu=cortex-a5 -o obj/startup_normal.o src/startup_normal.s
arm-none-eabi-as -mcpu=cortex-a5 -o obj/v7.o src/v7.s
When I try to compile v7.s I am getting the following errors as shown below:
src/v7.s: Assembler messages:
src/v7.s:1: Error: junk at end of line, first unrecognized character is `-'
src/v7.s:2: Error: bad instruction `v7-A Cache and Branch Prediction Maintenance Operations'
src/v7.s:3: Error: junk at end of line, first unrecognized character is `-'
src/v7.s:5: Error: bad instruction `preserve8 '
src/v7.s:7: Error: bad instruction `area v7Opps,CODE,READONLY'
src/v7.s:9: Error: junk at end of line, first unrecognized character is `-'
src/v7.s:10: Error: bad instruction `interrupt enable/disable'
src/v7.s:11: Error: junk at end of line, first unrecognized character is `-'
src/v7.s:13: Error: bad instruction `could use intrinsic instead of these'
src/v7.s:15: Error: bad instruction `export enableInterrupts'
src/v7.s:16: Error: bad instruction `void enableInterrupts(void)'
src/v7.s:17: Error: bad instruction `enableinterrupts PROC'
src/v7.s:20: Error: bad instruction `endp '
src/v7.s:22: Error: bad instruction `export disableInterrupts'
src/v7.s:23: Error: bad instruction `void disableInterrupts(void)'
src/v7.s:24: Error: bad instruction `disableinterrupts PROC'
src/v7.s:27: Error: bad instruction `endp '
src/v7.s:29: Error: junk at end of line, first unrecognized character is `-'
src/v7.s:30: Error: bad instruction `cache Maintenance'
src/v7.s:31: Error: junk at end of line, first unrecognized character is `-'
src/v7.s:33: Error: bad instruction `export enableCaches'
src/v7.s:34: Error: bad instruction `void enableCaches(void)'
src/v7.s:35: Error: bad instruction `enablecaches PROC'
src/v7.s:36: Error: bad instruction `read System Control Register configuration data'
src/v7.s:37: Error: bad instruction `set C bit'
src/v7.s:38: Error: bad instruction `set I bit'
src/v7.s:39: Error: bad instruction `write System Control Register configuration data'
src/v7.s:41: Error: bad instruction `endp '
src/v7.s:44: Error: bad instruction `export disableCaches'
src/v7.s:45: Error: bad instruction `void disableCaches(void)'
src/v7.s:46: Error: bad instruction `disablecaches PROC'
src/v7.s:47: Error: bad instruction `read System Control Register configuration data'
src/v7.s:48: Error: bad instruction `clear C bit'
src/v7.s:49: Error: bad instruction `clear I bit'
src/v7.s:50: Error: bad instruction `write System Control Register configuration data'
src/v7.s:52: Error: bad instruction `endp '
src/v7.s:55: Error: bad instruction `export cleanDCache'
src/v7.s:56: Error: bad instruction `void cleanDCache(void)'
src/v7.s:57: Error: bad instruction `cleandcache PROC'
src/v7.s:61: Error: bad instruction `based on code example given in section 11.2.4 of ARM DDI 0406B'
src/v7.s:64: Error: bad instruction `read CLIDR'
src/v7.s:66: Error: bad instruction `cache level value(naturally aligned)'
src/v7.s:70: Error: bad instruction `clean_dcache_loop1 '
src/v7.s:71: Error: bad instruction `work out 3xcachelevel'
src/v7.s:72: Error: bad instruction `bottom 3 bits are the Cache type for this level'
src/v7.s:73: Error: bad instruction `get those 3 bits alone'
src/v7.s:75: Error: bad instruction `no cache or only instruction cache at this level'
src/v7.s:76: Error: bad instruction `write the Cache Size selection register'
src/v7.s:77: Error: invalid barrier type -- `isb to sync the change to the CacheSizeID reg'
src/v7.s:78: Error: bad instruction `reads current Cache Size ID register'
src/v7.s:79: Error: bad instruction `extract the line length field'
src/v7.s:80: Error: ARM register expected -- `add 4 for the line length offset(log2 16 bytes)'
src/v7.s:82: Error: bad instruction `r4 is the max number on the way size(right aligned)'
src/v7.s:83: Error: bad instruction `r5 is the bit position of the way size increment'
src/v7.s:85: Error: bad instruction `r7 is the max number of the index size(right aligned)'
src/v7.s:87: Error: bad instruction `clean_dcache_loop2 '
src/v7.s:88: Error: bad instruction `r9 working copy of the max way size(right aligned)'
src/v7.s:90: Error: bad instruction `clean_dcache_loop3 '
src/v7.s:91: Error: bad instruction `factor in the way number and cache number into R11'
src/v7.s:92: Error: bad instruction `factor in the index number'
src/v7.s:93: Error: bad instruction `dccsw -clean by set/way'
src/v7.s:94: Error: bad instruction `decrement the way number'
src/v7.s:96: Error: bad instruction `decrement the index'
src/v7.s:99: Error: bad instruction `clean_dcache_skip '
src/v7.s:100: Error: bad instruction `increment the cache number'
src/v7.s:104: Error: bad instruction `clean_dcache_finished '
src/v7.s:108: Error: bad instruction `endp '
src/v7.s:110: Error: bad instruction `export cleanInvalidateDCache'
src/v7.s:111: Error: bad instruction `void cleanInvalidateDCache(void)'
src/v7.s:112: Error: bad instruction `cleaninvalidatedcache PROC'
src/v7.s:116: Error: bad instruction `based on code example given in section 11.2.4 of ARM DDI 0406B'
src/v7.s:119: Error: bad instruction `read CLIDR'
src/v7.s:121: Error: bad instruction `cache level value(naturally aligned)'
src/v7.s:125: Error: bad instruction `clean_invalidate_dcache_loop1 '
src/v7.s:126: Error: bad instruction `work out 3xcachelevel'
src/v7.s:127: Error: bad instruction `bottom 3 bits are the Cache type for this level'
src/v7.s:128: Error: bad instruction `get those 3 bits alone'
src/v7.s:130: Error: bad instruction `no cache or only instruction cache at this level'
src/v7.s:131: Error: bad instruction `write the Cache Size selection register'
src/v7.s:132: Error: invalid barrier type -- `isb to sync the change to the CacheSizeID reg'
src/v7.s:133: Error: bad instruction `reads current Cache Size ID register'
src/v7.s:134: Error: bad instruction `extract the line length field'
src/v7.s:135: Error: ARM register expected -- `add 4 for the line length offset(log2 16 bytes)'
src/v7.s:137: Error: bad instruction `r4 is the max number on the way size(right aligned)'
src/v7.s:138: Error: bad instruction `r5 is the bit position of the way size increment'
src/v7.s:140: Error: bad instruction `r7 is the max number of the index size(right aligned)'
src/v7.s:142: Error: bad instruction `clean_invalidate_dcache_loop2 '
src/v7.s:143: Error: bad instruction `r9 working copy of the max way size(right aligned)'
src/v7.s:145: Error: bad instruction `clean_invalidate_dcache_loop3 '
src/v7.s:146: Error: bad instruction `factor in the way number and cache number into R11'
src/v7.s:147: Error: bad instruction `factor in the index number'
src/v7.s:148: Error: bad instruction `dccisw -clean and invalidate by set/way'
src/v7.s:149: Error: bad instruction `decrement the way number'
src/v7.s:151: Error: bad instruction `decrement the index'
src/v7.s:154: Error: bad instruction `clean_invalidate_dcache_skip '
src/v7.s:155: Error: bad instruction `increment the cache number'
src/v7.s:159: Error: bad instruction `clean_invalidate_dcache_finished '
src/v7.s:163: Error: bad instruction `endp '
src/v7.s:166: Error: bad instruction `export invalidateCaches'
src/v7.s:167: Error: bad instruction `void invalidateCaches(void)'
src/v7.s:168: Error: bad instruction `invalidatecaches PROC'
src/v7.s:172: Error: bad instruction `based on code example given in section B2.2.4/11.2.4 of ARM DDI 0406B'
src/v7.s:176: Error: bad instruction `iciallu -Invalidate entire I Cache,and flushes branch target cache'
src/v7.s:178: Error: bad instruction `read CLIDR'
src/v7.s:180: Error: bad instruction `cache level value(naturally aligned)'
src/v7.s:184: Error: bad instruction `invalidate_caches_loop1 '
src/v7.s:185: Error: bad instruction `work out 3xcachelevel'
src/v7.s:186: Error: bad instruction `bottom 3 bits are the Cache type for this level'
src/v7.s:187: Error: bad instruction `get those 3 bits alone'
src/v7.s:189: Error: bad instruction `no cache or only instruction cache at this level'
src/v7.s:190: Error: bad instruction `write the Cache Size selection register'
src/v7.s:191: Error: invalid barrier type -- `isb to sync the change to the CacheSizeID reg'
src/v7.s:192: Error: bad instruction `reads current Cache Size ID register'
src/v7.s:193: Error: bad instruction `extract the line length field'
src/v7.s:194: Error: ARM register expected -- `add 4 for the line length offset(log2 16 bytes)'
src/v7.s:196: Error: bad instruction `r4 is the max number on the way size(right aligned)'
src/v7.s:197: Error: bad instruction `r5 is the bit position of the way size increment'
src/v7.s:199: Error: bad instruction `r7 is the max number of the index size(right aligned)'
src/v7.s:201: Error: bad instruction `invalidate_caches_loop2 '
src/v7.s:202: Error: bad instruction `r9 working copy of the max way size(right aligned)'
src/v7.s:204: Error: bad instruction `invalidate_caches_loop3 '
src/v7.s:205: Error: bad instruction `factor in the way number and cache number into R11'
src/v7.s:206: Error: bad instruction `factor in the index number'
src/v7.s:207: Error: bad instruction `dcisw -invalidate by set/way'
src/v7.s:208: Error: bad instruction `decrement the way number'
src/v7.s:210: Error: bad instruction `decrement the index'
src/v7.s:213: Error: bad instruction `invalidate_caches_skip '
src/v7.s:214: Error: bad instruction `increment the cache number'
src/v7.s:218: Error: bad instruction `invalidate_caches_finished '
src/v7.s:221: Error: bad instruction `endp '
src/v7.s:224: Error: bad instruction `export invalidateCaches_IS'
src/v7.s:225: Error: bad instruction `void invalidateCaches_IS(void)'
src/v7.s:226: Error: bad instruction `invalidatecaches_is PROC'
src/v7.s:230: Error: bad instruction `icialluis -Invalidate entire I Cache inner shareable'
src/v7.s:232: Error: bad instruction `read CLIDR'
src/v7.s:234: Error: bad instruction `cache level value(naturally aligned)'
src/v7.s:238: Error: bad instruction `invalidate_caches_is_loop1 '
src/v7.s:239: Error: bad instruction `work out 3xcachelevel'
src/v7.s:240: Error: bad instruction `bottom 3 bits are the Cache type for this level'
src/v7.s:241: Error: bad instruction `get those 3 bits alone'
src/v7.s:243: Error: bad instruction `no cache or only instruction cache at this level'
src/v7.s:244: Error: bad instruction `write the Cache Size selection register'
src/v7.s:245: Error: invalid barrier type -- `isb to sync the change to the CacheSizeID reg'
src/v7.s:246: Error: bad instruction `reads current Cache Size ID register'
src/v7.s:247: Error: bad instruction `extract the line length field'
src/v7.s:248: Error: ARM register expected -- `add 4 for the line length offset(log2 16 bytes)'
src/v7.s:250: Error: bad instruction `r4 is the max number on the way size(right aligned)'
src/v7.s:251: Error: bad instruction `r5 is the bit position of the way size increment'
src/v7.s:253: Error: bad instruction `r7 is the max number of the index size(right aligned)'
src/v7.s:255: Error: bad instruction `invalidate_caches_is_loop2 '
src/v7.s:256: Error: bad instruction `r9 working copy of the max way size(right aligned)'
src/v7.s:258: Error: bad instruction `invalidate_caches_is_loop3 '
src/v7.s:259: Error: bad instruction `factor in the way number and cache number into R11'
src/v7.s:260: Error: bad instruction `factor in the index number'
src/v7.s:261: Error: bad instruction `dcisw -clean by set/way'
src/v7.s:262: Error: bad instruction `decrement the way number'
src/v7.s:264: Error: bad instruction `decrement the index'
src/v7.s:267: Error: bad instruction `invalidate_caches_is_skip '
src/v7.s:268: Error: bad instruction `increment the cache number'
src/v7.s:272: Error: bad instruction `invalidate_caches_is_finished '
src/v7.s:275: Error: bad instruction `endp '
src/v7.s:277: Error: junk at end of line, first unrecognized character is `-'
src/v7.s:278: Error: bad instruction `tlb '
src/v7.s:279: Error: junk at end of line, first unrecognized character is `-'
src/v7.s:281: Error: bad instruction `export invalidateUnifiedTLB'
src/v7.s:282: Error: bad instruction `void invalidateUnifiedTLB(void)'
src/v7.s:283: Error: bad instruction `invalidateunifiedtlb PROC'
src/v7.s:285: Error: bad instruction `tlbiall -Invalidate entire unified TLB'
src/v7.s:287: Error: bad instruction `endp '
src/v7.s:289: Error: bad instruction `export invalidateUnifiedTLB_IS'
src/v7.s:290: Error: bad instruction `void invalidateUnifiedTLB_IS(void)'
src/v7.s:291: Error: bad instruction `invalidateunifiedtlb_is PROC'
src/v7.s:293: Error: bad instruction `tlbiallis -Invalidate entire unified TLB Inner Shareable'
src/v7.s:295: Error: bad instruction `endp '
src/v7.s:297: Error: junk at end of line, first unrecognized character is `-'
src/v7.s:298: Error: bad instruction `branch Prediction'
src/v7.s:299: Error: junk at end of line, first unrecognized character is `-'
src/v7.s:301: Error: bad instruction `export enableBranchPrediction'
src/v7.s:302: Error: bad instruction `void enable_branch_prediction(void)'
src/v7.s:303: Error: bad instruction `enablebranchprediction PROC'
src/v7.s:304: Error: bad instruction `read SCTLR'
src/v7.s:305: Error: bad instruction `set the Z bit(bit 11)'
src/v7.s:306: Error: bad instruction `write SCTLR'
src/v7.s:308: Error: bad instruction `endp '
src/v7.s:310: Error: bad instruction `export disableBranchPrediction'
src/v7.s:311: Error: bad instruction `void disableBranchPrediction(void)'
src/v7.s:312: Error: bad instruction `disablebranchprediction PROC'
src/v7.s:313: Error: bad instruction `read SCTLR'
src/v7.s:314: Error: bad instruction `clear the Z bit(bit 11)'
src/v7.s:315: Error: bad instruction `write SCTLR'
src/v7.s:317: Error: bad instruction `endp '
src/v7.s:319: Error: bad instruction `export flushBranchTargetCache'
src/v7.s:320: Error: bad instruction `void flushBranchTargetCache(void)'
src/v7.s:321: Error: bad instruction `flushbranchtargetcache PROC'
src/v7.s:323: Error: bad instruction `bpiall -Invalidate entire branch predictor array'
src/v7.s:325: Error: bad instruction `endp '
src/v7.s:327: Error: bad instruction `export flushBranchTargetCache_IS'
src/v7.s:328: Error: bad instruction `void flushBranchTargetCache_IS(void)'
src/v7.s:329: Error: bad instruction `flushbranchtargetcache_is PROC'
src/v7.s:331: Error: bad instruction `bpiallis -Invalidate entire branch predictor array Inner Shareable'
src/v7.s:333: Error: bad instruction `endp '
src/v7.s:335: Error: junk at end of line, first unrecognized character is `-'
src/v7.s:336: Error: bad instruction `high Vecs'
src/v7.s:337: Error: junk at end of line, first unrecognized character is `-'
src/v7.s:339: Error: bad instruction `export enableHighVecs'
src/v7.s:340: Error: bad instruction `void enableHighVecs(void)'
src/v7.s:341: Error: bad instruction `enablehighvecs PROC'
src/v7.s:342: Error: bad instruction `read Control Register'
src/v7.s:343: Error: bad instruction `set the V bit(bit 13)'
src/v7.s:344: Error: bad instruction `write Control Register'
src/v7.s:346: Error: bad instruction `endp '
src/v7.s:348: Error: bad instruction `export disableHighVecs'
src/v7.s:349: Error: bad instruction `void disable_highvecs(void)'
src/v7.s:350: Error: bad instruction `disablehighvecs PROC'
src/v7.s:351: Error: bad instruction `read Control Register'
src/v7.s:352: Error: bad instruction `clear the V bit(bit 13)'
src/v7.s:353: Error: bad instruction `write Control Register'
src/v7.s:355: Error: bad instruction `endp '
src/v7.s:357: Error: junk at end of line, first unrecognized character is `-'
src/v7.s:358: Error: bad instruction `context ID'
src/v7.s:359: Error: junk at end of line, first unrecognized character is `-'
src/v7.s:361: Error: bad instruction `export getContextID'
src/v7.s:362: Error: bad instruction `uint32_t getContextIDd(void)'
src/v7.s:363: Error: bad instruction `getcontextid PROC'
src/v7.s:364: Error: bad instruction `read Context ID Register'
src/v7.s:366: Error: bad instruction `endp '
src/v7.s:368: Error: bad instruction `export setContextID'
src/v7.s:369: Error: bad instruction `void setContextID(uint32_t)'
src/v7.s:370: Error: bad instruction `setcontextid PROC'
src/v7.s:371: Error: bad instruction `write Context ID Register'
src/v7.s:373: Error: bad instruction `endp '
src/v7.s:375: Error: junk at end of line, first unrecognized character is `-'
src/v7.s:376: Error: bad instruction `id registers'
src/v7.s:377: Error: junk at end of line, first unrecognized character is `-'
src/v7.s:379: Error: bad instruction `export getMIDR'
src/v7.s:380: Error: bad instruction `uint32_t getMIDR(void)'
src/v7.s:381: Error: bad instruction `getmidr PROC'
src/v7.s:382: Error: bad instruction `read Main ID Register(MIDR)'
src/v7.s:384: Error: bad instruction `endp '
src/v7.s:386: Error: bad instruction `export getMPIDR'
src/v7.s:387: Error: bad instruction `uint32_t getMPIDR(void)'
src/v7.s:388: Error: bad instruction `getmpidr PROC'
src/v7.s:389: Error: bad instruction `read Multiprocessor ID register(MPIDR)'
src/v7.s:391: Error: bad instruction `endp '
src/v7.s:393: Error: junk at end of line, first unrecognized character is `-'
src/v7.s:394: Error: bad instruction `cp15 SMP related'
src/v7.s:395: Error: junk at end of line, first unrecognized character is `-'
src/v7.s:397: Error: bad instruction `export getBaseAddr'
src/v7.s:398: Error: bad instruction `uint32_t getBaseAddr(void)'
src/v7.s:399: Error: bad instruction `returns the value CBAR(base address of the private peripheral memory space)'
src/v7.s:400: Error: bad instruction `getbaseaddr PROC'
src/v7.s:401: Error: bad instruction `read periph base address(see DE593076)'
src/v7.s:403: Error: bad instruction `endp '
src/v7.s:405: Error: junk at end of line, first unrecognized character is `-'
src/v7.s:407: Error: bad instruction `export getCPUID'
src/v7.s:408: Error: bad instruction `uint32_t getCPUID(void)'
src/v7.s:409: Error: bad instruction `returns the CPU ID(0 to 3)of the CPU executed on'
src/v7.s:410: Error: bad instruction `getcpuid PROC'
src/v7.s:411: Error: bad instruction `read CPU ID register'
src/v7.s:412: Error: bad instruction `mask off,leaving the CPU ID field'
src/v7.s:414: Error: bad instruction `endp '
src/v7.s:416: Error: junk at end of line, first unrecognized character is `-'
src/v7.s:418: Error: bad instruction `export goToSleep'
src/v7.s:419: Error: bad instruction `void goToSleep(void)'
src/v7.s:420: Error: bad instruction `gotosleep PROC'
src/v7.s:421: Error: bad instruction `go into standby'
src/v7.s:422: Error: bad instruction `catch in case of rogue events'
src/v7.s:424: Error: bad instruction `endp '
src/v7.s:426: Error: junk at end of line, first unrecognized character is `-'
src/v7.s:428: Error: bad instruction `export joinSMP'
src/v7.s:429: Error: bad instruction `void joinSMP(void)'
src/v7.s:430: Error: bad instruction `sets the ACTRL.SMP bit'
src/v7.s:431: Error: bad instruction `joinsmp PROC'
src/v7.s:433: Error: bad instruction `smp status is controlled by bit 6 of the CP15 Aux Ctrl Reg'
src/v7.s:435: Error: bad instruction `read ACTLR'
src/v7.s:436: Error: bad instruction `set bit 6'
src/v7.s:437: Error: bad instruction `write ACTLR'
src/v7.s:440: Error: bad instruction `endp '
src/v7.s:442: Error: junk at end of line, first unrecognized character is `-'
src/v7.s:444: Error: bad instruction `export leaveSMP'
src/v7.s:445: Error: bad instruction `void leaveSMP(void)'
src/v7.s:446: Error: bad instruction `clear the ACTRL.SMP bit'
src/v7.s:447: Error: bad instruction `leavesmp PROC'
src/v7.s:449: Error: bad instruction `smp status is controlled by bit 6 of the CP15 Aux Ctrl Reg'
src/v7.s:451: Error: bad instruction `read ACTLR'
src/v7.s:452: Error: bad instruction `clear bit 6'
src/v7.s:453: Error: bad instruction `write ACTLR'
src/v7.s:456: Error: bad instruction `endp '
src/v7.s:458: Error: junk at end of line, first unrecognized character is `-'
src/v7.s:459: Error: bad instruction `end of code'
src/v7.s:460: Error: junk at end of line, first unrecognized character is `-'
src/v7.s:462: Error: bad instruction `end '
src/v7.s:464: Error: junk at end of line, first unrecognized character is `-'
src/v7.s:465: Error: bad instruction `end of v7.s'
src/v7.s:466: Error: junk at end of line, first unrecognized character is `-'
src/v7.s:65: Error: invalid operands (*GAS `expr' section* and *ABS* sections) for `&'
src/v7.s: Error: can't resolve value for symbol `L0 '
src/v7.s:79: Error: invalid operands (*GAS `expr' section* and *ABS* sections) for `&'
src/v7.s:120: Error: invalid operands (*GAS `expr' section* and *ABS* sections) for `&'
src/v7.s:134: Error: invalid operands (*GAS `expr' section* and *ABS* sections) for `&'
src/v7.s:179: Error: invalid operands (*GAS `expr' section* and *ABS* sections) for `&'
src/v7.s:193: Error: invalid operands (*GAS `expr' section* and *ABS* sections) for `&'
src/v7.s:233: Error: invalid operands (*GAS `expr' section* and *ABS* sections) for `&'
src/v7.s:247: Error: invalid operands (*GAS `expr' section* and *ABS* sections) for `&'
Please guide me on how to resolve this error. Whether this v7.s file applicable to armv7-a ?
Please suggest me how to cross compile this example for ARMv7-a using command line.
Please guide me how to link scatter_normal.txt for "arm-none-eabi-" tool chain.
Regards,
Ajith
Thank you for the response.
As suggested I have modified v7.s and tried to compile.
Now, when I try to perform the following command as shown below in the command line.
arm-none-eabi-ld -scatter=scatter_normal.txt --entry=normalStart -o normal.axf ./obj/main_normal.o ./obj/retarget_normal.o ./obj/startup_normal.o ./obj/v7.o
arm-none-eabi-ld: cannot open linker script file atter=scatter_normal.txt: No such file or directory
I can see that scatter_normal.txt file is present in the same folder.
Do I need to modify scatter_normal.txt file?
Please suggest me in this regard.
Hi Ajith,
Now that you're done with converting armasm syntax to GNU assembler syntax, you need to convert armlink scatter files into GNU ld scripts... joy!
The scatter files are thankfully really simple, and your ld script should be quite simple to match. Note, though, that Martin's assertion that you'll have to deal with the ARM C library functionality comes into play here, in that "ARM_LIB_STACKHEAP" is a special symbol that only really applies to the ARM C library. For whatever library (newlib?) you're using to cross-compile the application, you'll have to somehow else define the stack and heap locations.
Also note that the memory locations are entirely ARM EB-specific (and Versatile Express-specific for the other example). You'll have to modify them for your actual target as you go.
There are plenty of examples online on GNU ld scripting..
Ta,
Matt
Thank you for the support.
As I am a new to this, can you please guide me in converting a sample scatter_normal.txt file into a sample GNU ld script. So that it can help me in converting scatter_secure.txt file.
I will modify the memory locations in the ld script as per the actual target.
ajithkumsi,
ARM generally don't provide "coding help" at this level - perhaps someone else in the forum can assist.
Essentially, though, the LD script and scatter file are doing the same job. They provide addresses which links certain objects and section types into a final executable. For instance:
NORMAL_LOAD 0x100000{ NORMAL_EXE 0x100000 0xA0000 { startup_normal.o(NormalStartUp, +FIRST)
NORMAL_LOAD 0x100000
{
NORMAL_EXE 0x100000 0xA0000
startup_normal.o(NormalStartUp, +FIRST)
ARM scatter files define a "Load Region" and an "Execution Region". Scatterloading is just an ARM term for "relocation" of the "Load Region" data to the "Execution Region" - in this case it's defining a segment called NORMAL_LOAD with a section NORMAL_EXE at address 0x100000 (for both, so there would be no memory copy involved). It also dictates that the function "NormalStartUp" within the object file "startup_normal.o" is placed in this section, and that function should be first in the section. 0xA0000 is the maximum size of the section.
It maps fairly well to ELF program headers and section headers, respectively, and tells the linker what to do. You can get the same effect with GNU ld, just without the benefit of the magical implementation of "Scatterloading" (code relocation is usually a job for the target system, in this case the ARM C Library implements it, but 'newlib' or 'uclibc' might not do it at all, or do it very differently).
If you're having trouble mapping these concepts in, give us an example and we may be able to give a direct answer, but we can't port the script for you. Again, there are some very helpful people here who may be able to give you some more dedicated support.