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ARMv8中的Non-cacheable transaction

Yu2017

在CA53的TRM中，关于ACE transfer有以下描述

For Non-cacheable transactions:
• INCR N (N:1, 2, or 4) 128-bit for write transfers.

想请教一下，CPU中执行什么样的指令，会在总线上产生 INCR4 128bit的write transfer

多谢！

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