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如何理解PoC,CCN-5xx中的L3如何maintenance?

Hi ARM专家们,有几个问题请教一下:

1、PoC是所有Agents能看到同一个memory copy的点,通常是external memory;CCN-5xx HN-F中实现了PoC,

      用于管理RN-Fs间的coherency,假如CPU发出带PoC属性的cache maintenance操作,是否可以maintenance L3?

2、如果CPU发出的是带PoU但是带Inner-Shareable属性的cache maintenance操作,此时是否会maintenance L3?

      因为CPU接口规定,如果是BROADCASTINNER=1,则BROADCASTOUTER也必须是1。

3、CCN-5xx L3中特别注明指令是pseudo-inclusive,这个与inclusive差别在哪呢?

4、DEN0024A_v8_architecture_PG.pdf文档p214,Table 14-1中,用Set/Way来maintenance cache不带Broadcast

     可以理解,但为啥DC IVAC, Xt是一定Broadcast,而DC CVAC, Xt仅是Maybe Broadcast?

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