This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

关于neon汇编的几个问题

1.VMLAL.I16  这条指令I16是的意思是可能是S16或者是U16吗? 如果有个数是S16,有个数是U16,这两个数相乘可以使用I16吗??

2. 

Vopn{cond}.datatype list, [Rn{@align}]{!}

Q1:文档中说到 “Align 可省略。 在这种情况下,将应用标准对齐规则”。 这里的标准对齐规则是什么样的?

Q2:如果Rn地址没有按照Q1中提到的标准对齐规则, 那么load数据的时候是否会出错还是说效率降低?

Q3:如果已经确定Rn是按照256bit对齐,那么指令vld1.32 {d0}, [r0:256] 是否会比vld1.32 {d0}, [r0] 效率高?

Parents
  • 1.VMLAL

    对于该指令,数据类型必须是下列中的一种:

    I8, I16, I32, F32 for VMUL, VMLA, or VMLS

    S8, S16, S32 for VMULL, VMLAL, or VMLSL

    U8, U16, U32 for VMULL, VMLAL, or VMLSL

    P8 for VMUL or VMULL.

    也就是说要么是S16, 要么是U16, 不支持I16。如果想要S16XU16,需要确定U16的范围,看是否能将其视为S16。

    2. 

    Vopn{cond}.datatype list, [Rn{@align}]{!}

    Q1:文档中说到 “Align 可省略。 在这种情况下,将应用标准对齐规则”。 这里的标准对齐规则是什么样的?

    Q2:如果Rn地址没有按照Q1中提到的标准对齐规则, 那么load数据的时候是否会出错还是说效率降低?

    ARM® Compiler toolchain

    Version 5.02

    Assembler Reference

    4.10 Alignment restrictions in load and store, element and structure instructions

    Many of these instructions permit memory alignment restrictions to be specified. When the

    alignment is not specified in the instruction, the alignment restriction is controlled by the A bit

    (SCTLR bit[1]):

    • if the A bit is 0, there are no alignment restrictions (except for strongly ordered or device

    memory, where accesses must be element aligned or the result is UNPREDICTABLE)

    • if the A bit is 1, accesses must be element aligned.

    If an address is not correctly aligned, an alignment fault occurs

    Q3:如果已经确定Rn是按照256bit对齐,那么指令vld1.32 {d0}, [r0:256] 是否会比vld1.32 {d0}, [r0] 效率高?

    如果Rn确定是256bit对齐,加上对齐标志比不加效率高。

Reply
  • 1.VMLAL

    对于该指令,数据类型必须是下列中的一种:

    I8, I16, I32, F32 for VMUL, VMLA, or VMLS

    S8, S16, S32 for VMULL, VMLAL, or VMLSL

    U8, U16, U32 for VMULL, VMLAL, or VMLSL

    P8 for VMUL or VMULL.

    也就是说要么是S16, 要么是U16, 不支持I16。如果想要S16XU16,需要确定U16的范围,看是否能将其视为S16。

    2. 

    Vopn{cond}.datatype list, [Rn{@align}]{!}

    Q1:文档中说到 “Align 可省略。 在这种情况下,将应用标准对齐规则”。 这里的标准对齐规则是什么样的?

    Q2:如果Rn地址没有按照Q1中提到的标准对齐规则, 那么load数据的时候是否会出错还是说效率降低?

    ARM® Compiler toolchain

    Version 5.02

    Assembler Reference

    4.10 Alignment restrictions in load and store, element and structure instructions

    Many of these instructions permit memory alignment restrictions to be specified. When the

    alignment is not specified in the instruction, the alignment restriction is controlled by the A bit

    (SCTLR bit[1]):

    • if the A bit is 0, there are no alignment restrictions (except for strongly ordered or device

    memory, where accesses must be element aligned or the result is UNPREDICTABLE)

    • if the A bit is 1, accesses must be element aligned.

    If an address is not correctly aligned, an alignment fault occurs

    Q3:如果已经确定Rn是按照256bit对齐,那么指令vld1.32 {d0}, [r0:256] 是否会比vld1.32 {d0}, [r0] 效率高?

    如果Rn确定是256bit对齐,加上对齐标志比不加效率高。

Children