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Cortex-A7 burst transaction question

hi, experts:

我想在CA7 平台上,使用 LDMIA / STMID to produce some continual burst memory transactions.

CA7的DCache line = 64bytes(512bit)

因此,如果我确保访问的目的地址,是64bytes对齐的,那么就会产生burst memory transactions,对吗?

比如:

LDMIA R10, {R0-R5}

如果R10=0x1000,就会产生burst memory read transaction.

假定选择AXI Bus width = 64bit,那么上述LDMIA指令,就会产生3个64bit read burst transaction.

best wishes,