Arm Community
Site
Search
User
Site
Search
User
Groups
Education Hub
Distinguished Ambassadors
Open Source Software and Platforms
Research Collaboration and Enablement
Forums
AI and ML forum
Architectures and Processors forum
Arm Development Platforms forum
Arm Development Studio forum
Arm Virtual Hardware forum
Automotive forum
Compilers and Libraries forum
Graphics, Gaming, and VR forum
High Performance Computing (HPC) forum
Infrastructure Solutions forum
Internet of Things (IoT) forum
Keil forum
Morello forum
Operating Systems forum
SoC Design and Simulation forum
SystemReady Forum
Blogs
AI and ML blog
Announcements
Architectures and Processors blog
Automotive blog
Graphics, Gaming, and VR blog
High Performance Computing (HPC) blog
Infrastructure Solutions blog
Internet of Things (IoT) blog
Operating Systems blog
SoC Design and Simulation blog
Tools, Software and IDEs blog
Support
Arm Support Services
Documentation
Downloads
Training
Arm Approved program
Arm Design Reviews
Community Help
More
Cancel
Support forums
中文社区论区
cache misses
Jump...
Cancel
State
Accepted Answer
Locked
Locked
Replies
4 replies
Subscribers
7 subscribers
Views
16360 views
Users
0 members are here
Cache
Options
Share
More actions
Cancel
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion
cache misses
zhangyumao
over 6 years ago
Support for three outstanding data cache misses？
请问这句话是什么意思呢？
Top replies
william gao
over 6 years ago
+4
verified
这是cache硬件设计细节的参数，能减少pipeline停顿，增加L1 cache回填的带宽。 当L1 cache miss之后，cache控制逻辑会访问下级memory进行回填，这往往非常耗时，并且cache会block住后续的pipeline对cache的访问，从而使得memory访问延迟直接对pipeline可见。CPU支持3个outstanding cache miss，表示CPU可以在cache...
Parents
0
Zhongwei Yao
over 6 years ago
in reply to
william gao
OK, 大概理解了。多谢。
Cancel
Up
0
Down
Cancel
Reply
0
Zhongwei Yao
over 6 years ago
in reply to
william gao
OK, 大概理解了。多谢。
Cancel
Up
0
Down
Cancel
Children
No data