• Locked Locked
  • Replies 3 replies
  • Subscribers 8 subscribers
  • Views 5480 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

官方手册cache数据错误

zhangyumao

如图：

 按照计算256 index的话，256*64Byte*4=65536Byte，算出来是64KB的cache，但是这里说的是32KB，是官网数据有误还是我算错了？

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/ch11s01s02.html

Parents

  • It may be a typo and should be 2-way set.  If we consider the description text for this Figure 11.4, we can see

    "

    A simplified four-way set associative 32KB L1 cache (such as the data cache of the Cortex-A57
    processor), with a 16-word (64 byte) cache line length, is shown in Figure 11-4:

    "

    But for Cortex-A57, its L1 data cache is 2-way set 32KB, not 4-way set.

Reply

  • It may be a typo and should be 2-way set.  If we consider the description text for this Figure 11.4, we can see

    "

    A simplified four-way set associative 32KB L1 cache (such as the data cache of the Cortex-A57
    processor), with a 16-word (64 byte) cache line length, is shown in Figure 11-4:

    "

    But for Cortex-A57, its L1 data cache is 2-way set 32KB, not 4-way set.

Children