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What happens if ITCM and DTCM overlap on ARM926EJ-S?

Frédéric Hoguin
Note: This was originally posted on 23rd January 2012 at http://forums.arm.com

Hello,

I noticed a bug in ITCM and DTCM initialization in some bootloader code.

The result is that the same value is written in the ITCM region register  and in the DTCM region register, so both are configured with the same  address and size.

It looks like in this case, ITCM gets priority over DTCM since  everything is working correctly when executing code stored in this  region of memory. If DTCM had priority, fetching an instruction from  this region of memory would cause a prefetch abort exception.

Now, that's my understanding of what happens, but I couldn't find anything about it in the ARM926EJ-S documentation.

Can anybody confirm my theory, or explain what happens in detail?

Thanks,

Frédéric.
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  • Note: This was originally posted on 23rd January 2012 at http://forums.arm.com

    It is probably luck that it works.

    From memory, instruction fetches will go to the ITCM, and data accesses to the DTCM.  (Note I don't think it is documented anywhere that it does this, all the docs I've seen just say not to do this). So it will work if you have no data in the ITCM.  Sounds easy, but remember that compilers often embed pools of literal data within instruction sections.  Basically, its a bad idea to map them to the same address.
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  • Note: This was originally posted on 23rd January 2012 at http://forums.arm.com

    It is probably luck that it works.

    From memory, instruction fetches will go to the ITCM, and data accesses to the DTCM.  (Note I don't think it is documented anywhere that it does this, all the docs I've seen just say not to do this). So it will work if you have no data in the ITCM.  Sounds easy, but remember that compilers often embed pools of literal data within instruction sections.  Basically, its a bad idea to map them to the same address.
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