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Does the NVIC really do interrupt nesting?

Konstantin Dimitrov
Note: This was originally posted on 23rd February 2011 at http://forums.arm.com

For days I've been banging my head with a problem that shouldn't take more than a minute time otherwise. How to get the NVIC of Cortex M3 handle the simplest in the world interrupt nesting - an interrupt within interrupt.
In details - I have the SysTick running that executes my handling function. What I am trying to achieve is to re-enable the SysTick interrupt and let the same function be executed should another SysTick has occured while it was still serving the previous one. With the old "dumb" ARM7's VIC that was the easiest thing to do - just enabling the interrupts again once I've entered my function. But with this "advanced" one, a person apparently has to go through some tricks to get the job done.
Any help would be warmly welcome!
Thanks
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  • Note: This was originally posted on 24th February 2011 at http://forums.arm.com


    I can't even say whether you could trick the NVIC into doing anything like this, since I have never been in a situation where this seemed to be the best solution. Could you describe a scenario where this would be necessary?

    Regards
    Marcus



    Sure. I am porting my own in-house RTOS kernel that uses task scheduling based on stacking. It has been working great for years on the old ARM7 machines and many other CPUs, even some PICs. Having an interrupt within interrupt is among the simplest things a modern CPU could do. The whole story develops around the fact I can execute the stack from within itself with the currently pending tasks. I take care myself about the stack overflow but I simply need the ability to re-enable the same interrupt and let it be served while I am still in it.
    CM3 is the first CPU I've ever sen that seems to disable this functionality but I really hope someone will prove me wrong as I am very much a noob with this one.
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  • Note: This was originally posted on 24th February 2011 at http://forums.arm.com


    I can't even say whether you could trick the NVIC into doing anything like this, since I have never been in a situation where this seemed to be the best solution. Could you describe a scenario where this would be necessary?

    Regards
    Marcus



    Sure. I am porting my own in-house RTOS kernel that uses task scheduling based on stacking. It has been working great for years on the old ARM7 machines and many other CPUs, even some PICs. Having an interrupt within interrupt is among the simplest things a modern CPU could do. The whole story develops around the fact I can execute the stack from within itself with the currently pending tasks. I take care myself about the stack overflow but I simply need the ability to re-enable the same interrupt and let it be served while I am still in it.
    CM3 is the first CPU I've ever sen that seems to disable this functionality but I really hope someone will prove me wrong as I am very much a noob with this one.
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