when I say partial word access, I mean 16-bit (two byte) or 8-bit (byte) read/write.
Background: In one of our recent projects, Cyclone V SoC is used to replace 386 CPU in an existing product. I am responsible for the board and FPGA design. Another software engineer is developing software under DS5 environment. Avalon MM Slave interface is use on FPGA side. Software needs to read/write data on the FPGA.
Problem description: Everything works fine on Altera System Console. However, it does not work so well on DS5. I have problem with the addresses that are not multiple of 4. For example, it works for address 0x800, I can read a full 32-bit word, or a 16-bit half-word, or a single byte. But for address 0x802, I cannot read out anything. All I got is all zeros.
Troubleshooting being conducted: I thought it relates to where the data should be put on the 32bit data bus. So I revised FPGA code to duplicate the data on the 32-bit bus, but DS5 still reads all zeros. Also tried to run SignalTap to capture waveforms, but DS5 and SignalTap cannot be run at the same time through the same JTAG connector.
anybody know what could be the problem?
Hi qsxiang,
I am not an expert in FPGA/Avalon, I'm just interested with what you are doing and your current problem.
Avalon supports aligned accesses only. For address 0x802 you should not perform a full 32-bit word access. The problem now reduces to 16-bit half-word or a single byte read if you get all zeroes.
The cause of the problem is quite obscure since Avalon's system interconnect fabric does most of the work and only few set(s) of signals are left to connect to the master and slave. In fact, the Avalon-MM interface for fixed-cycle read and write transfers appears simple.
Duplicating the data for half-word and byte reads may seem a nice try to diagnose the problem. However, replication of data on the bus is done in systems where misaligned data transfer is supported, bus width is asymmetric, or bus width of slave is not known in advance. Avalon's system interconnect fabric has a knowledge about the properties of masters and slaves and replication of data may not be needed since logic can be built to route the data to the proper byte lanes.
Since there is little detail that you provided, I'll suggest that you verify how you deal with endianness, hardware and/or software. Although, this might not be the cause of the problem because you can properly read data for address 0x800, and you also tried duplication of data, it might help if you review how you handle this property. Avalon is little-endian, depending on the ARM core that you are using, your processor's bus may be compatible with Avalon or may need remapping from big-endianness.
Finally, these questions may also help find the fault:
What's the value of the addressUnits property? How do you use the address (especially bits 1 and 0) and byteenable signals? Are you using native address alignment or dynamic bus sizing? Native addressing is already deprecated, but might be still supported by the tools that you have.
Regards,
Goodwin
Thanks, Goodwin.
I have resolved the problem yesterday. I will update the post in the community.
The problem is with the byteenable signal generated by the AXI-Avalon bridge. It is asserted to correct value for only one clock cycle.
To access address 0x802, the byteenable needs to be “1100”, and it should maintain the same value during the entire transaction. However, it only stay effective for one clock cycle then changed to different value.
I have to revise my FPGA code to latch the byteenable signal, and use the latched value in my FPGA logic.
The Avalon Master used by Altera System Console generates the correct byteenable signal during the entire transaction. So that is why my FPGA works well on System Console, but failed on DS-5.
Qiangsheng Xiang
Senior Engineer
GE Hitachi Nuclear Energy America
910-819-6344 (work)
910-233-2985 (cell)
Congrats Qiangsheng! You resolved it and I appreciate your feedback info about the status of your project.