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FVP_MPS: Write Byte Not Working for The 7-Segmenet Display?

Meng-Yuan Huang

My simulation environment is: uVision 5.14 + Fast Models 9.2

The fixed virtual platform is this one:

C:\FastModelsPortfolio_9.2\examples\FVP_MPS\Build_Cortex-M4\FVP_MPS_Cortex-M4.sgproj

I want to write a program to control the 7-segmenet displays. By Fast Models Version 9.2 Reference Manual page 8-397, the 7-segment display register is at 0x40004010. The display 0 is at 0x40004010, the display 1 is at 0x40004011, the display 2 is at 0x40004012, and the display 3 is at 0x40004013. I want to control only the display 0, so I wrote the code:

volatile unsigned char* SEVEN_SEG_BASE = (volatile unsigned char*) 0x40004010;

*SEVEN_SEG_BASE = 0xFF;

Unfortuately, running this code resulted in the excpetion: HardFault_Handler.

Then, I changed the data type char to int:

volatile unsigned int* SEVEN_SEG_BASE = (volatile unsigned int*) 0x40004010;

and run the code again, it worked well. I am confused that I can use "volatile unsigned char*" to send data to UART, however, why I can't use this data type to write the 7-segment display. What's the reason?

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  • 0

    Device control registers are typically mapped to word addresses in ARM Cortex-M products and should be accessed using the register length. On x86 byte sized control registers may be a byte apart and I guess you thought the individual bytes of the 7-segment display register were individual control registers. They aren't - the 4-digit display is updated as a unit. In other cases you might find byte or halfword sized control registers a word apart. There is no guarantee of a hard fault if the access size is wrong - the effect could be undefined but it certainly is much better if a chip detects the problem so it is caught early on. I think the word alignment was based on some ancient hardware problem but it has been turned into a sort of feature so bi-endian access works well with practicaly zero hardware support and without swapping the registers around.

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  • 0

    Device control registers are typically mapped to word addresses in ARM Cortex-M products and should be accessed using the register length. On x86 byte sized control registers may be a byte apart and I guess you thought the individual bytes of the 7-segment display register were individual control registers. They aren't - the 4-digit display is updated as a unit. In other cases you might find byte or halfword sized control registers a word apart. There is no guarantee of a hard fault if the access size is wrong - the effect could be undefined but it certainly is much better if a chip detects the problem so it is caught early on. I think the word alignment was based on some ancient hardware problem but it has been turned into a sort of feature so bi-endian access works well with practicaly zero hardware support and without swapping the registers around.

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