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Some questions of AXI

Note: This was originally posted on 14th November 2011 at http://forums.arm.com

>>In AMBA4 AXI rev 2.0, in chapter 4.1 About addressing options:
>>Burst must not cross 4KB boundaries to prevent them from crossing boundaries between slaves and to limit the size of the address incrementer required within slaves.
Is it mean there use 20 bits to decode which slave is selected?

>>In chapter 9.2 Write strobes:
>>The write strobe signals, WSTRB, enable sparse data transfer on the write data bus.
I don't know what is this sentence mean. anybody can explanation detail, thanks!!
  • Note: This was originally posted on 14th November 2011 at http://forums.arm.com

    > Is it mean there use 20 bits to decode which slave is selected?

    Yes, if your smallest slaves are as small as 4K in size.

    >>The write strobe signals, WSTRB, enable sparse data transfer on the write data bus.
    > I don't know what is this sentence mean. anybody can explanation detail, thanks!!

    It just means that not all the byte lanes of the data bus specified by AWADDR/AWSIZE will be used in the "sparse" data transfer.

    An example would be AWADDR=0x0, AWSIZE=3'b011 (8 byte transfer width), but WSTRB=0x11001001. AWSIZE says that 8 bytes could be transferred, but WSTRB indicates that only byte lanes 7, 6, 3 and 0 are actually used.

    AWSIZE will be constant for a burst, but WSTRB can change on each data transfer, so it gives quite a flexible way of signalling which bytes to update in a target when using a burst.

    Simple masters will not use "sparse" transfers, and will just drive all the relevant WSTRB bits high for each transfer in a burst. Note that AWSIZE tells you the maximum number of WSTRB bits you can assert, so for example if you were performing a byte transfer (AWSIZE=3'b000) on a 64 bit data bus, you could only assert 1 WSTRB bit.

    JD
  • Note: This was originally posted on 15th November 2011 at http://forums.arm.com

    Hello JD,
    thanks for your reply, it's really help me! thanks again.