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TrustZone with PL310

syuji biwa
Note: This was originally posted on 17th August 2013 at http://forums.arm.com

I plan to use a simple 'TrustZone Monitor'  with PL310(L2CC).
In non-secure, I will play a Linux-Kernel.

One problem.
1. PL310's background-operation(inv.way etc..)  is executing in non-secure.
2. By secure-interrupt, dispatch to secure.
3. In secure, try to execute a write-operation to PL310' register.
May be happen 'DATA-ABORT'.

Do I must control exclusive PL310  secure and non-secure ?

Please help me.
Parents
  • Note: This was originally posted on 20th August 2013 at http://forums.arm.com

    Well as I mentioned in my last post, to meet the spec for the L2CC operations you have to guarantee that you don't access memory ranges which may be in a cache way which is being cleaned by a background operation. [color=#222222][font=Arial, Helvetica, sans-serif][size=2]In general it the therefore _impossible_ to run arbitrary code while a background operation is running; you can pretty much guarantee you will touch at least one of the locked ways. This therefore means you to disable interrupts, etc, while performing background operations and stop other cores running which could touch the cache.[/size][/font][/color]
    [color=#222222][font=Arial, Helvetica, sans-serif][size=2]
    [/size][/font][/color]
    [color=#222222][font=Arial, Helvetica, sans-serif][size=2]Again, it is very [/size][/font][/color][color=#222222][font=Arial, Helvetica, sans-serif][size=2]unusual[/size][/font][/color][color=#222222][font=Arial, Helvetica, sans-serif][size=2] for code to want to nuke the whole cache, precisely because it is very hard to make safe; for full SMP systems the atomic set-way instructions exist.[/size][/font][/color]
    [color=#222222][font=Arial, Helvetica, sans-serif][size=2]
    [/size][/font][/color]
    [color=#222222][font=Arial, Helvetica, sans-serif][size=2]HTH,
    Iso[/size][/font][/color]
Reply
  • Note: This was originally posted on 20th August 2013 at http://forums.arm.com

    Well as I mentioned in my last post, to meet the spec for the L2CC operations you have to guarantee that you don't access memory ranges which may be in a cache way which is being cleaned by a background operation. [color=#222222][font=Arial, Helvetica, sans-serif][size=2]In general it the therefore _impossible_ to run arbitrary code while a background operation is running; you can pretty much guarantee you will touch at least one of the locked ways. This therefore means you to disable interrupts, etc, while performing background operations and stop other cores running which could touch the cache.[/size][/font][/color]
    [color=#222222][font=Arial, Helvetica, sans-serif][size=2]
    [/size][/font][/color]
    [color=#222222][font=Arial, Helvetica, sans-serif][size=2]Again, it is very [/size][/font][/color][color=#222222][font=Arial, Helvetica, sans-serif][size=2]unusual[/size][/font][/color][color=#222222][font=Arial, Helvetica, sans-serif][size=2] for code to want to nuke the whole cache, precisely because it is very hard to make safe; for full SMP systems the atomic set-way instructions exist.[/size][/font][/color]
    [color=#222222][font=Arial, Helvetica, sans-serif][size=2]
    [/size][/font][/color]
    [color=#222222][font=Arial, Helvetica, sans-serif][size=2]HTH,
    Iso[/size][/font][/color]
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