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TrustZone with PL310
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TrustZone with PL310
syuji biwa
over 10 years ago
Note: This was originally posted on 17th August 2013 at
http://forums.arm.com
I plan to use a simple 'TrustZone Monitor' with PL310(L2CC).
In non-secure, I will play a Linux-Kernel.
One problem.
1. PL310's background-operation(inv.way etc..) is executing in non-secure.
2. By secure-interrupt, dispatch to secure.
3. In secure, try to execute a write-operation to PL310' register.
May be happen 'DATA-ABORT'.
Do I must control exclusive PL310 secure and non-secure ?
Please help me.
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syuji biwa
over 10 years ago
Note: This was originally posted on 20th August 2013 at
http://forums.arm.com
I'm sorry, I'm mistake.
My question is only by the multi-core system.
The last example was not good.
A suitable example :
core0:
SecureOS (I plan to create this.)
core1:
Non-secureOS (Linux)
Is exclusive control required for PL310 between SecureOS and Non-secureOS?
If true, do SpinLock need to implemented between SecureOS and Non-secureOS?
Common memory required for SpinLock?
And, one more question.
If SecureOS uses L1-cache only(L1:cacheable L2:non-cacheable page),
L2-cache-sync-operation require?
For example (PL310 enabled)
DMA transfer.
1. write to normal-memory.
2. DMB execute.
3. write to DMA register(device-memory).
4. DSB execute.
Does PL310 always write in as turn? (1->3)
Or Turn is not guaranteed?
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syuji biwa
over 10 years ago
Note: This was originally posted on 20th August 2013 at
http://forums.arm.com
I'm sorry, I'm mistake.
My question is only by the multi-core system.
The last example was not good.
A suitable example :
core0:
SecureOS (I plan to create this.)
core1:
Non-secureOS (Linux)
Is exclusive control required for PL310 between SecureOS and Non-secureOS?
If true, do SpinLock need to implemented between SecureOS and Non-secureOS?
Common memory required for SpinLock?
And, one more question.
If SecureOS uses L1-cache only(L1:cacheable L2:non-cacheable page),
L2-cache-sync-operation require?
For example (PL310 enabled)
DMA transfer.
1. write to normal-memory.
2. DMB execute.
3. write to DMA register(device-memory).
4. DSB execute.
Does PL310 always write in as turn? (1->3)
Or Turn is not guaranteed?
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