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Dear Experts
I am working on a target that contains quad A53 cores operating at 1GHz. The operating system idle loop contains WFI inline assembly instruction. I know that the Core Clock halts during the WFI instruction which can be seen on the PM_CCNTR counts.
I was thinking if I can utilize this fact to get some figures around the system cpu_load. The idea is if I am sampling the PM_CCNTR on a regular bases with time stamp. I can use these time stamps to calculate the diff time between to consecutive samples. do the PM_CCNTR diff value can be indicative to the cpuload?
example: if I am sampling every 10ms seconds I should expect 10,000,000 counts if the core utilization is 100%. If I got 7,000,000 this means that the core spent 30% of the time in the idle loop. hence, the cpu load should be 70%.
Note: there is no where else on the code where WFI is been used.
My question: Is this methodology make sense? Is there any thing that could alter the core clock other than the WFI instruction? What else should I take into account?
What do you mean by throttling the cpu exactly? If you mean decrease the core clock input, is that doable on the Cortex-A53?
Anyway, the operating system I use does not do that at all.