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Translation error at level1 in armv8 A72 cortex

Hi,

I am trying to enable MMU on LS1046ARDB using baremetal boot code . We are translating 1GB of DRAM as NORMAL READ WRITE memory . We are able to load entries into translation tables successfully . But as soon as MMU is enabled the execution is crashing and we are getting translation error at level 1 indicated in IFSC Field of ESR_EL3 Register.(Error code : 0x86000005)

Attached below is the assembly code we are using to set up Translation tables and enable MMU.

Are we missing anything? Any suggestions would be appreciated.

 

Thanks,

Faizanbaig Inamdar

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/*
* This file was automatically generated using arm64-pgtable-tool.
* See: https://github.com/ashwio/arm64-pgtable-tool
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* This code programs the following translation table structure:
*
* level 1 table @ 0x80000000
* [# 2]---------------------------\
* level 2 table @ 0x80001000
* [# 128] 0x000090000000-0x0000901fffff, RW_Data, DRAM
* [# 129] 0x000090200000-0x0000903fffff, RW_Data, DRAM
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

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