Hi,
I am getting started with armv8-a and I need some help.
I am trying to understand how cache memories work and I am looking specifically at this code:
https://github.com/rsta2/circle/blob/master/boot/armstub/armstub8.S
There is a reference to register S3_1_C11_C0_2 which I don't see mentioned in the whole ARMARM document. I am doing a text search on the PDF document so I may have missed it.
Does anyone know where documentation about it can be found?
Thanks
Checkout Cortex-A53 TRM.
Hi yaw moo,
42Bastian Schick is right, the L2CTLR_EL1 is described in the Cortex-A53 TRM; see L2 Control Register.