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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3581 Questions
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  • Answered

    I have a question about cache operations. +1

    2019 views
    5 replies
    Latest over 3 years ago
    by YP.Lu
  • Not Answered

    Devices that Implement and Develop ARM Trustzone 0

    1766 views
    2 replies
    Latest over 3 years ago
    by Hayes169
  • Not Answered

    LDR instruction not executing 0

    • 5 (BusFault)
    • 3 (HardFault)
    • Compilers
    • Cortex-M4
    3281 views
    3 replies
    Latest over 3 years ago
    by alexxs88
  • Not Answered

    Load-Exclusive and Store-Exclusive usage confusion 0

    1884 views
    1 reply
    Latest over 3 years ago
    by Annie
  • Not Answered

    Which version of NIC support AMBA5? 0

    1398 views
    1 reply
    Latest over 3 years ago
    by Annie
  • Not Answered

    Cortex-R52 SPI interrupt routing to PEs not working 0

    2294 views
    3 replies
    Latest over 3 years ago
    by Lukas Rohrwild
  • Answered

    Enable/Disable L2 cache on ARM Cortex-A72 0

    • Cortex-A72
    3362 views
    4 replies
    Latest over 3 years ago
    by Chanh
  • Not Answered

    pl230 r0p0 dma controller 0

    1472 views
    0 replies
    Started over 3 years ago
    by Deepak Bose
  • Suggested Answer

    Set stack size in linker file for Cortex-A72 0

    3146 views
    6 replies
    Latest over 3 years ago
    by Chanh
  • Suggested Answer

    What is "AXI Ordering Model" in AXI4?? 0

    • AXI
    • AXI4
    2825 views
    1 reply
    Latest over 3 years ago
    by a.surati
  • Not Answered

    question about DAP-LITE 0

    • CoreSight Debug Access Port Lite (DAP-Lite)
    2227 views
    3 replies
    Latest over 3 years ago
    by Dibbert
  • Not Answered

    Set A72 frequency to fixed speed 0

    • Cortex-A72
    • AArch64
    • Armv8-A
    1837 views
    3 replies
    Latest over 3 years ago
    by 42Bastian Schick
  • Not Answered

    A description of each of the pipeline stages / ARMv9 Cortex-A510 0

    2766 views
    3 replies
    Latest over 3 years ago
    by 42Bastian Schick
  • Suggested Answer

    force the toolchain to only use Thumb-16 in M0/3/4 0

    • GCC
    • Compilers
    • Cortex-M
    • GNU Toolchain
    2506 views
    3 replies
    Latest over 3 years ago
    by 42Bastian Schick
  • Answered

    Inexplicable synchronous exceptions from EL0 0

    • ARMv8 Exception Model
    • Armv8-A
    3087 views
    2 replies
    Latest over 3 years ago
    by MrMino
  • Answered

    Request for suggesting Android Automotive 12 supported boards +1

    2824 views
    2 replies
    Latest over 3 years ago
    by Ronan Synnott Arm Employee Badge
  • Suggested Answer

    runtime in cortex M4 0

    1569 views
    3 replies
    Latest over 3 years ago
    by GBS
  • Answered

    How writing ICC_EOIR1_EL1 works for Group 1 Interrupts when running on EL3 in GICv3? 0

    • GICv3/v4
    • ARMv8 Exception Model
    • Armv8-A
    • TrustZone
    1862 views
    2 replies
    Latest over 3 years ago
    by MHesham
  • Answered

    TTBR0_EL1 translation fault level 3 on 4KiB blocks where 2MiB blocks work. 0

    • Armv8-A
    • System MMU
    3762 views
    3 replies
    Latest over 3 years ago
    by a.surati
  • Answered

    TTBR0_EL1, translation fault level 0 after switching identity mapping off 0

    • Armv8-A
    4696 views
    6 replies
    Latest over 3 years ago
    by MrMino
<>
Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
  • Armv8-M
  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
  • Cortex-A7
  • Cortex-A8
  • Cortex-A9
  • Cortex-M
  • Cortex-M0
  • Cortex-M3
  • Cortex-M4
  • Cortex-M7
  • Cortex-R
  • Interrupt
  • Linux
  • Memory
  • Memory Management Unit (MMU)
  • NEON
  • TrustZone