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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3579 Questions
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  • Answered

    Does CCI-400 guarantees cache coherency between secure and non-secure worlds? 0

    • Cortex-A53
    • Cortex-A57
    • big.LITTLE
    • CoreLink CCI-400
    • Cache
    • Cortex-A
    5345 views
    3 replies
    Latest over 10 years ago
    by Kay
  • Not Answered

    ARM Context ID Register & Process Context Switch 0

    • Armv7-A
    • Cortex-A9
    • Cortex-A
    • Cortex-A8
    17534 views
    10 replies
    Latest over 10 years ago
    by onion
  • Answered

    Reordering between multiple loads 0

    • Cache
    • Cortex-A
    • Cortex-A8
    7759 views
    7 replies
    Latest over 10 years ago
    by Hemant
  • Answered

    How can we boot linux kernel in ARM FVP w/ TrustZone? 0

    • Cortex-A9
    • Cortex-A
    • TrustZone
    • Linux
    8608 views
    4 replies
    Latest over 10 years ago
    by Yoshiharu Imamoto
  • Not Answered

    Is First-level table skippable? (VMSA) 0

    • Cortex-A17
    • AArch64
    • Cortex-A15
    • Cortex-A
    • Cortex-A7
    • AArch32
    7999 views
    4 replies
    Latest over 10 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    Cortex-R5 and Cortex-R7 implement as Dual-Core Lock Step (DCLS), does the two core run inparallel? +1

    • Processor
    • Cortex-R
    • Cortex-A
    7707 views
    2 replies
    Latest over 10 years ago
    by 42Bastian
  • Answered

    How should I do if I want to enable only one single CPU on a Cortex A9 MPCore(2 CPUs) +1

    • Cortex-A9
    • Cortex-A15
    • Cache
    • Cortex-A
    • Linux
    4658 views
    1 reply
    Latest over 10 years ago
    by 박주병
  • Answered

    How to set inner of outer shareability on page table entry WITHOUT TEX remap?? 0

    • Cortex-A
    • TrustZone
    6701 views
    3 replies
    Latest over 10 years ago
    by Matt Sealey Arm Employee Badge
  • Answered

    If non-secure world pass to virtual address (allocated by malloc or mmap) and ttbr value, how to find valid physical address in secure-world 0

    • Cortex-A53
    • Cortex-A57
    • Cortex-A
    6641 views
    3 replies
    Latest over 10 years ago
    by Axel Heider
  • Answered

    ARM v8 Arch SCTLR bit field meaning 0

    • EL1
    • EL2
    • AArch64
    8298 views
    4 replies
    Latest over 10 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    ACE-Lite Master and Slaves 0

    • AMBA
    • AXI4
    • ACE-Lite
    5113 views
    2 replies
    Latest over 10 years ago
    by Uma
  • Answered

    The madman strikes again - ADD/SUB SP 0

    • Thumb
    • Cortex-A
    • Cortex-A7
    6097 views
    9 replies
    Latest over 10 years ago
    by Juha Aaltonen
  • Answered

    ASR #32 0

    • Cortex-A
    • Cortex-A7
    9147 views
    10 replies
    Latest over 10 years ago
    by Jens Bauer
  • Answered

    SMMU initialization +1

    • Cortex-A
    • Cortex-A7
    8455 views
    2 replies
    Latest over 10 years ago
    by Dav
  • Answered

    If the mispredict happen, is there a mechanism to abort the instructions(have been fetched or decoded)? 0

    • Cortex-A
    4197 views
    3 replies
    Latest over 10 years ago
    by Peter Harris Arm Employee Badge
  • Answered

    How does the BTIC(branch target instruction cache) works? 0

    • Cache
    • Cortex-A
    • Cortex-A7
    15891 views
    3 replies
    Latest over 10 years ago
    by Hanni Lozano
  • Answered

    Software Radio Based on ZedBoard and AD-FMCOMMS1-EBZ +1

    • Cortex-A9
    • Cortex-A
    • Linux
    8818 views
    3 replies
    Latest over 10 years ago
    by hgli
  • Answered

    The cortex-A7's pipeline support dual-issue, so I want to ask what's the dual-issue mean? 0

    • NEON
    • Cortex-A
    • Cortex-A7
    10406 views
    4 replies
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Answered

    How to measure program execution time in ARM Cortex-A53 processor? +1

    • Cortex-A53
    • Cortex-A57
    • AArch64
    • Cortex-A15
    • Armv8-A
    • Cortex-A
    12835 views
    2 replies
    Latest over 10 years ago
    by Rajeev Verma
  • Answered

    Pseudocode for saturation (Oh no, not again) 0

    • Cortex-A
    • Cortex-A7
    4029 views
    2 replies
    Latest over 10 years ago
    by Juha Aaltonen
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Topics being discussed in this forum
  • AArch64
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  • Armv7-A
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  • Linux
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  • NEON
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