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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3622 Questions
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  • Answered

    SMC flow on ARMv8 0

    • ARMv8 Exception Model
    • Armv8-A
    7050 views
    1 reply
    Latest over 8 years ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    AXI write outstanding transactions causing problem in image data 0

    • AMBA 3
    6035 views
    1 reply
    Latest over 8 years ago
    by petehaw Arm Employee Badge
  • Answered

    Transition to secure monitor flow on ARMv8 0

    • ARMv8 Exception Model
    • Armv8
    • Armv8-A
    • Cortex-A
    • Cotex-A72
    • Baremetal
    7393 views
    4 replies
    Latest over 8 years ago
    by Umair Khan
  • Suggested Answer

    Stable set of ARM MCU, libraries, and Dev Environment 0

    • Keil
    • IDEs and Tool Suites
    • Cortex-M
    • Software Development
    6867 views
    5 replies
    Latest over 8 years ago
    by Sebastian Floss
  • Not Answered

    Using st1 to copy 3 floats from NEON register 0

    3943 views
    2 replies
    Latest over 8 years ago
    by lefty
  • Not Answered

    Purpose of SAU in Multi-Master System 0

    • ACE
    • Security
    • TrustZone
    • System Design
    • Community
    • Armv8-M
    • Secure Transactions
    • Memory
    9053 views
    1 reply
    Latest over 8 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    ARM Cortex-A53 System Register +1

    • Cortex-A53
    5976 views
    4 replies
    Latest over 8 years ago
    by M1509
  • Answered

    When to enable ARM Cortex A8 L1 cache parity detection 0

    4407 views
    3 replies
    Latest over 8 years ago
    by 42Bastian Schick
  • Answered

    Cortex A9 (IMX6) : Enabling branch prediction aborts +1

    13611 views
    10 replies
    Latest over 8 years ago
    by Gopu
  • Answered

    Multiple voltage levels for a Single Frequency in ARM A15 processors +1

    4382 views
    2 replies
    Latest over 8 years ago
    by 42Bastian Schick
  • Not Answered

    configuration clock using CMSIS stm32f7 ? 0

    3428 views
    1 reply
    Latest over 8 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    hello , How to enable / disable a global interrupt on cortex M7 +1

    • Interrupt
    30012 views
    1 reply
    Latest over 8 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    Ignored bits in ARMv7a LPAE / ARMv8 Table descriptors 0

    5543 views
    4 replies
    Latest over 8 years ago
    by Vincent Siles
  • Suggested Answer

    Hardfault issue 0

    5298 views
    4 replies
    Latest over 8 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    ARMv7 Vs ARMv8 AArch32 Performance improvement +2

    • Armv7
    • Armv8
    • AArch32
    17368 views
    5 replies
    Latest over 8 years ago
    by damalinxp
  • Answered

    Questions regarding NEON 0

    • DSP
    • NEON
    6892 views
    3 replies
    Latest over 8 years ago
    by gravi
  • Answered

    Instruction Fetches from Peripheral Memory Space 0

    • ACE
    • TrustZone
    • Instruction Fetch
    • Armv8-M
    • Memory
    16240 views
    6 replies
    Latest over 8 years ago
    by Diya Soubra Arm Employee Badge
  • Not Answered

    Core definition is missing - Cortex-R5 (reconfiguring database) 0

    • DS-5 Community Edition
    3016 views
    1 reply
    Latest over 8 years ago
    by Joseph Yiu Arm Employee Badge
  • Not Answered

    DIscussion, Cortex-a53 support pthread with 4 cores work together 0

    7165 views
    3 replies
    Latest over 8 years ago
    by 42Bastian Schick
  • Answered

    NIC-400 remapping +1

    5176 views
    1 reply
    Latest over 8 years ago
    by fengxg001
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