Cortex M4 L1 data cache policy

I have some confusions about the difference between write back + write allocate and write back + write no allocate on Cortex CM4.

As my original understanding:

• For write back with write allocate:
  • If write-address isn't cache hinted yet, cache line will be allocated and filled, data is written to cache line but real physical device
  • If write-address is hinted yet, data will be written to cache line but real physical device.
• For write back with write no allocate
  • If write-address isn't  hinted, no cache line will be allocated, data will be pushed to device directly.
  • If write-address is hinted, data will be written to cache line but device

But i see such description in Cortex-A7 TRM:

"All Inner Write-Back memory is treated as Write-Back Write-Allocate ignoring any cache
allocate hint, though this can dynamically switch to no write-allocate, if more than three
full cache lines are written in succession."

Seems write back with write allocate is almost same with write back with write no allocate on CA7? I didn't see similar description on CM4, CA9 and CA53 TRM. What's the behavior for write back with write allocate/non allocate on CA9, CA53 and CM4?