I have some confusions about the difference between write back + write allocate and write back + write no allocate on Cortex CM4.
As my original understanding:
But i see such description in Cortex-A7 TRM:
"All Inner Write-Back memory is treated as Write-Back Write-Allocate ignoring any cacheallocate hint, though this can dynamically switch to no write-allocate, if more than threefull cache lines are written in succession."
Seems write back with write allocate is almost same with write back with write no allocate on CA7? I didn't see similar description on CM4, CA9 and CA53 TRM. What's the behavior for write back with write allocate/non allocate on CA9, CA53 and CM4?
For Cortex-M4, there is no internal cache and cache hint instructions are executed as NOPs (no operations). Therefore this is no such description in Cortex-M4 TRM. However, it does export cacheable attribute to the bus (AHB Lite + additional memory attribute sideband). How the cache attributes are handled is up to the system level cache design.
Sorry that I don't have the answers for Cortex-A9 and A53.