Arm Community
Arm Community
  • Site
  • User
  • Site
  • Search
  • User
Support forums
Support forums
Architectures and Processors forum
  • Jump...
  • Cancel
  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3581 Questions
Help a member

Have a question? If you can, please take a moment to also see if there is a question that you are able to answer.

  • Tags
  • RSS
  • More actions
  • Cancel
Other forums
  • AI forum

  • Architectures and Processors forum

  • Arm Development Platforms forum

  • Arm Development Studio forum

  • Arm Virtual Hardware forum

  • Automotive forum

  • Compilers and Libraries forum

  • Embedded and Microcontrollers forum

  • High Performance Computing (HPC) forum

  • Internet of Things (IoT) forum

  • Keil forum

  • Laptops and Desktops forum

  • Mobile, Graphics, and Gaming forum

  • Morello forum

  • Operating Systems forum

  • Servers and Cloud Computing forum

  • SoC Design and Simulation forum

  • SystemReady Forum

  • Not Answered

    Cortex M1 only runs in debugger (using ARTIX-7) 0

    3445 views
    3 replies
    Latest over 6 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    Best ARM processor for a low power medical device +1

    • Cortex-M
    4855 views
    1 reply
    Latest over 6 years ago
    by Ben Walshe Arm Employee Badge
  • Answered

    Best Microbenchmark package for Arm Cortex-A9 +1

    16280 views
    1 reply
    Latest over 6 years ago
    by vstehle Arm Employee Badge
  • Answered

    Attempt to set Secure Privileged Mode in armv7 A8 (using am3358 BBB silicon)? 0

    • Armv7-A
    • Secure Transactions
    17116 views
    3 replies
    Latest over 6 years ago
    by _nobody_
  • Not Answered

    Context protection when calling a secure function(NSC) in a non-secure interrupt function 0

    19814 views
    10 replies
    Latest over 6 years ago
    by Yang Zhang
  • Answered

    Dual core cortex-m7 for security applications +2

    • Cortex-M7
    • Cortex-M
    6101 views
    3 replies
    Latest over 6 years ago
    by Joseph Yiu Arm Employee Badge
  • Not Answered

    TCM arbitration hazard: Considerations for Firmware 0

    • Cortex-R
    • Cortex-R5
    2212 views
    0 replies
    Started over 6 years ago
    by c0deface
  • Answered

    IRQ in c++ not redirecting correct address +1

    3301 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    volatile variable position in the stack (ABI std) +1

    5392 views
    5 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    Synchronization of caches on ARMv8 0

    • Armv8-A
    18018 views
    2 replies
    Latest over 6 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    ARMCC V6.12 problem with simple std::queue +1

    3360 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Not Answered

    SIMD-NEON Optimization on CortexA7or Cortex A57 0

    • SIMD and Vector Processing Instructions
    15866 views
    1 reply
    Latest over 6 years ago
    by br-dev
  • Answered

    How to Change the Non Secure VTOR (Cortex-M33) +1

    • TrustZone for Armv8-M
    • Trusted Execution Environment (TEE)
    • TrustZone
    • Cortex-M33
    • Armv8-M
    11498 views
    5 replies
    Latest over 6 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    Flushing all L1 & L2 caches under Linux (kernel space) - optimizing dma-mapping API 0

    • Cortex-A9
    • DMA Devices
    • Linux
    24942 views
    2 replies
    Latest over 6 years ago
    by eli.z
  • Answered

    What is the "Integer divide unit with support for operand-dependent early termination"? +1

    • Cortex-M
    • Cortex-M33
    4243 views
    1 reply
    Latest over 6 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    How to import C variable in an assembly code in a .s file +1

    • Cortex-M
    • Cortex-M0+
    • Arm Assembly Language (ASM)
    8316 views
    2 replies
    Latest over 6 years ago
    by Joseph Yiu Arm Employee Badge
  • Not Answered

    How to place FreeRTOS in secure memory and the user tasks in non-secure memory? 0

    • TrustZone
    • Armv8-M
    43179 views
    21 replies
    Latest over 6 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    how to understand L1 cache but L2 & L3 non-cached +1

    • L1
    • L3
    • Cortex-A55
    • Cache
    • Cortex-A
    • L2
    21464 views
    4 replies
    Latest over 6 years ago
    by phil9980
  • Answered

    Cortex R5 behavior when a masked imprecise/asynchronous abort occurs +1

    9679 views
    6 replies
    Latest over 6 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    GICv3 Group0 secure interrupts routed to monitor when running in S-EL1 0

    • EL1
    • EL3
    • GICv3/v4
    • Interrupt
    16515 views
    2 replies
    Latest over 6 years ago
    by odeprez
<>
Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
  • Armv8-M
  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
  • Cortex-A7
  • Cortex-A8
  • Cortex-A9
  • Cortex-M
  • Cortex-M0
  • Cortex-M3
  • Cortex-M4
  • Cortex-M7
  • Cortex-R
  • Interrupt
  • Linux
  • Memory
  • Memory Management Unit (MMU)
  • NEON
  • TrustZone