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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3629 Questions
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  • Answered

    Why is the cycle count for running the same instruction multiple times not linearly increasing on the STM32F4? 0

    • Arm Assembly Language (ASM)
    • Cortex-M4
    • STM32 F4
    6711 views
    10 replies
    Latest over 4 years ago
    by PatrickG
  • Not Answered

    Help to debug boot issue 0

    • Cortex-A53
    • a64
    3577 views
    3 replies
    Latest over 4 years ago
    by Zhifei Yang Arm Employee Badge
  • Not Answered

    which GPU driver is suitable for an aarch64 CPU? 0

    1533 views
    1 reply
    Latest over 4 years ago
    by Oliver Beirne Arm Employee Badge
  • Not Answered

    Coredump backtrace frames 0

    3368 views
    1 reply
    Latest over 4 years ago
    by Zhifei Yang Arm Employee Badge
  • Answered

    ARM Exception Levels remain same for all ARM architectures? +1

    1791 views
    2 replies
    Latest over 4 years ago
    by Manjunath Kalmath
  • Not Answered

    STR755FV1T6 - hw/sw connectivity solution advice/help needed 0

    1518 views
    1 reply
    Latest over 4 years ago
    by Zhifei Yang Arm Employee Badge
  • Answered

    Which GNU Toolchain for A - profile Architecture to be used? 0

    1779 views
    2 replies
    Latest over 4 years ago
    by Manjunath Kalmath
  • Suggested Answer

    Linux kernel boot-up issue in ARM Cortex-A78 while accessing virtual memory 0

    • Kernel Developers
    • Armv8-A
    • Memory Management Unit (MMU)
    • Cortex-A78
    5330 views
    5 replies
    Latest over 4 years ago
    by selgan01 Arm Employee Badge
  • Answered

    R5 MPU Background Region +1

    • Cortex-R5
    2732 views
    4 replies
    Latest over 4 years ago
    by ijahmad
  • Suggested Answer

    Where is 'The level associated with MMU faults' referenced multiple times in Exception Register documentation 0

    • AArch64
    • Documentation
    • Memory Management Unit (MMU)
    3110 views
    2 replies
    Latest over 4 years ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    How are packets routed from a master to the correct slave in a multi-slave AXI system? 0

    • AXI4
    1977 views
    1 reply
    Latest over 4 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Undeterministic behaviour of memcpy using NEON registers 0

    • AArch64
    • NEON
    • Memory Access Instructions
    4365 views
    3 replies
    Latest over 4 years ago
    by Zenon (Zhilong) Xiu Arm Employee Badge
  • Not Answered

    Assigning bit to GPIO stm32 0

    1915 views
    3 replies
    Latest over 4 years ago
    by 42Bastian Schick
  • Not Answered

    Cortex M33 SWCLK faster than CLKIN for CortexM33 0

    • Cortex-M33
    1068 views
    0 replies
    Started over 4 years ago
    by RPP
  • Not Answered

    R5 MPU regions 0

    • R5
    2244 views
    2 replies
    Latest over 4 years ago
    by ijahmad
  • Answered

    Boot from BL2->BL31->Linux 0

    6440 views
    5 replies
    Latest over 4 years ago
    by HeavyLamb
  • Not Answered

    Atomic instruction(e.g. LDXR, STXR) can't execute by CPU Cortex-A78 0

    • Kernel Developers
    • U-Boot
    • Cortex-A
    2914 views
    4 replies
    Latest over 4 years ago
    by Romit Patel
  • Not Answered

    Differences between "LDR r4, =0x50013ffc " and making the address 0x50013ffc using several instructions in thumb16- cortex M3 0

    1401 views
    1 reply
    Latest over 4 years ago
    by 42Bastian Schick
  • Not Answered

    What are the characteristics of the two? 0

    1379 views
    1 reply
    Latest over 4 years ago
    by 42Bastian Schick
  • Answered

    Linux offline individual non boot CPU in SMP cortex-CA7 0

    2500 views
    3 replies
    Latest over 4 years ago
    by ilchang
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