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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3593 Questions
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  • Answered

    What is the internal fault of 0xb42293? +1

    4298 views
    1 reply
    Latest over 8 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    Clarity on EDBGRQ on CM4 +1

    4490 views
    1 reply
    Latest over 8 years ago
    by Joseph Yiu Arm Employee Badge
  • Not Answered

    A couple of use cases for TrustZone for ARMv8-M 0

    • Bluetooth
    • Architecture
    • ACE
    • CHI
    • Security
    • Cortex-M
    • TrustZone
    • Armv8-M
    • Software Development
    • Memory
    9738 views
    1 reply
    Latest over 8 years ago
    by Diya Soubra Arm Employee Badge
  • Not Answered

    What is the software overhead for TrustZone for ARMv8-M? 0

    • ANSI
    • Security
    • TrustZone
    • Armv8-M
    7406 views
    0 replies
    Started over 8 years ago
    by Diya Soubra Arm Employee Badge
  • Not Answered

    What is the top level difference in features between Cortex-M23 and Cortex-M33? 0

    • Cortex-M23
    • Cortex-M3
    • Cortex-M
    • TrustZone
    • Cortex-M33
    • Armv8-M
    9849 views
    0 replies
    Started over 8 years ago
    by Diya Soubra Arm Employee Badge
  • Not Answered

    Which of the Cortex-M processors support TrustZone for ARMv8-M today? 0

    • Cortex-M23
    • Cortex-M3
    • Cortex-M
    • TrustZone
    • Cortex-M33
    • Armv8-M
    7435 views
    0 replies
    Started over 8 years ago
    by Diya Soubra Arm Employee Badge
  • Not Answered

    What is TrustZone for ARMv8-M? 0

    • CHI
    • Security
    • Cortex-M3
    • Cortex-A
    • Cortex-M
    • TrustZone
    • Cortex-M33
    • Armv8-M
    • Software Development
    12733 views
    0 replies
    Started over 8 years ago
    by Diya Soubra Arm Employee Badge
  • Answered

    Linker in gnu arm toolchain says "group ended without start" thought there is no such option in my build +1

    • Toolchain
    • Embedded Software
    • GCC
    • Thumb
    • GNU Arm
    • Cortex-M
    • Cortex-M4
    8966 views
    5 replies
    Latest over 8 years ago
    by Thomas Preudhomme Arm Employee Badge
  • Suggested Answer

    Cortex A53 Program Counter Load After Debug Exit 0

    6487 views
    2 replies
    Latest over 8 years ago
    by Michael Williams Arm Employee Badge
  • Answered

    Is there an atomic way to enable the MMU and continue at a given virtual address +1

    4627 views
    1 reply
    Latest over 8 years ago
    by Ash Wilding Arm Employee Badge
  • Answered

    What's happening if NMI is active (via a push-button) during µC (Cortex M4) start-up (power on)? +2

    • Cortex-M
    • Cortex-M4
    7835 views
    3 replies
    Latest over 8 years ago
    by Jerome Decamps - 杜尚杰
  • Suggested Answer

    What's implemented in STM32F103C8? 0

    5030 views
    1 reply
    Latest over 8 years ago
    by Yasuhiko Koumoto
  • Answered

    thumb 2 instruction set 0

    12395 views
    7 replies
    Latest over 8 years ago
    by cray
  • Suggested Answer

    Can Cortex M7 AXI master interface generate interleaved writes to the same slave? 0

    5035 views
    3 replies
    Latest over 8 years ago
    by Diandian Zhang
  • Answered

    What does the assertion "AXI_ERRS_BRESP_ALL_DONE_EOS" in "AMBA 3 AXI Protocol Checker User Guide" mean? 0

    4846 views
    2 replies
    Latest over 8 years ago
    by Diandian Zhang
  • Answered

    Delay Subroutine LPC2148 Assembly +1

    • Arm7
    • GPIO
    • Arm Assembly Language (ASM)
    12569 views
    3 replies
    Latest over 8 years ago
    by Yasuhiko Koumoto
  • Not Answered

    ARM Cortex Educational Courses 0

    2914 views
    1 reply
    Latest over 8 years ago
    by Mark Nicholson Arm Employee Badge
  • Suggested Answer

    How to make sure L2CC won't make any data write interleave request? 0

    3377 views
    1 reply
    Latest over 8 years ago
    by Yasuhiko Koumoto
  • Answered

    armv5TE +1

    • Armv5T
    • Armv5TE
    • Armv5
    7458 views
    3 replies
    Latest over 8 years ago
    by kalle
  • Answered

    when and where will the LDP instruction trigger an exception ? 0

    8915 views
    6 replies
    Latest over 8 years ago
    by daith
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Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
  • Armv8-M
  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
  • Cortex-A7
  • Cortex-A8
  • Cortex-A9
  • Cortex-M
  • Cortex-M0
  • Cortex-M3
  • Cortex-M4
  • Cortex-M7
  • Cortex-R
  • Interrupt
  • Linux
  • Memory
  • Memory Management Unit (MMU)
  • NEON
  • TrustZone