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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3593 Questions
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  • Answered

    Multi core L1 cache coherent +1

    • Cortex-A53
    • Armv8-A
    • Cortex-A
    7053 views
    3 replies
    Latest over 7 years ago
    by Jorney
  • Answered

    What ARMv8.x revision Cortex-A35 is? 0

    • Cortex-A35
    • Armv8-A
    • Cortex-A
    5283 views
    1 reply
    Latest over 7 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    Why Cortex-M7 doesn't support bit-banding? 0

    • Cortex-M7
    • Cortex-M
    10518 views
    2 replies
    Latest over 7 years ago
    by Joseph Yiu Arm Employee Badge
  • Suggested Answer

    ARMv8-A CurrentEL Register Definition 0

    • Cortex-A53
    • Armv8-A
    • Cortex-A
    9709 views
    1 reply
    Latest over 7 years ago
    by kuksho
  • Suggested Answer

    Arm a53: Populate TLB without table walk? 0

    • Cortex-A53
    • Cortex-A
    4335 views
    1 reply
    Latest over 7 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    MMU: force identity mapping without pages? 0

    • Cortex-A53
    • Memory Management Unit (MMU)
    • Cortex-A
    13714 views
    14 replies
    Latest over 7 years ago
    by MarkL
  • Not Answered

    The process of initializing ddr and other things on Cortex-A9 0

    • Cortex-A9
    • JTAG
    • Cortex-A
    4003 views
    0 replies
    Started over 7 years ago
    by Dean_Runov
  • Not Answered

    Juno r2 and Xen 0

    • Juno Arm Development Platform
    5338 views
    0 replies
    Started over 7 years ago
    by Fresher
  • Not Answered

    Cortex-A53 Cache protection 0

    • Cortex-A53
    • Cache
    • Cortex-A
    4570 views
    0 replies
    Started over 7 years ago
    by iuli
  • Answered

    Cortex M7 D cache activated without MPU been enabled +1

    • Cortex-M7
    • Cortex-M
    5176 views
    1 reply
    Latest over 7 years ago
    by vishal.s
  • Answered

    single-copy atomicity question for AHB5 0

    • AMBA 5
    • AHB
    8024 views
    2 replies
    Latest over 7 years ago
    by Jacky Chou
  • Answered

    ARMV8-M CPU State when secure API called by none-secure irq +1

    • TrustZone
    • Armv8-M
    7632 views
    2 replies
    Latest over 7 years ago
    by rising
  • Suggested Answer

    Does Documents have release Notes or update history? 0

    • Cortex-M3
    • Cortex-M
    4579 views
    2 replies
    Latest over 7 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    Cortex-R5: Data abort handling 0

    • Cortex-R
    • Cortex-R5
    • C
    10152 views
    5 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Answered

    Could anybody tell me how to boot up a processor in AARCH32 bit mode in Arm V8 and A53 core? 0

    • Cortex-A53
    • Armv8-A
    • Cortex-A
    • AArch32
    10502 views
    3 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Suggested Answer

    Using PMU on cortex-a9 CPU 0

    • Cortex-A9
    • Cortex-A
    11863 views
    10 replies
    Latest over 7 years ago
    by vstehle Arm Employee Badge
  • Answered

    Disabling PFU / instruction pre-fetch on Cortex-R4? +1

    • Cortex-R
    • Cortex-R5
    • Cache
    7432 views
    4 replies
    Latest over 7 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    about cortex-A72 0

    • Cortex-A72
    • Cortex-A
    6741 views
    5 replies
    Latest over 7 years ago
    by vstehle Arm Employee Badge
  • Answered

    Change Vector Table in cortex M4 in a persistent way 0

    • Cortex-M
    • Cortex-M4
    5858 views
    4 replies
    Latest over 7 years ago
    by EA8
  • Suggested Answer

    the means of tail-chaining of interrupts 0

    • Embedded
    • Cortex-M3
    • Cortex-M
    • Software Development
    11488 views
    1 reply
    Latest over 7 years ago
    by Stuart Shepherd Arm Employee Badge
<>
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