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aarch64 kernel using aarch32 page tables

Vincent Siles

Hi !

I'm trying to update my custom kernel, working with short or long descriptor in armv7a to a target supporting armv8.

My current setup uses TTBR0 to point to the PL0 page table and TTBR1 to point to the PL1 page table.

At the moment, I sometimes use the PL0 bindings to write data from PL1  to PL0 (kernel space to user space), for example when I create a new process and copy the ELF code/data into userspace.

My first attempt is to update my kernel to run in EL1 aarch64 mode, and keep my applications in EL0 aarch32 mode. To keep the same behavior (using EL0 bindings at EL1), I think I have to use long aarch64 descriptor for EL0. So my question is:

While at EL1 aarch64 (using TTBR1 to map the kernel), can I point TTBR0 to a aarch32 long descriptor table to be able to access user data using PL0 bindings ?

  • +1

    hi siles,

      I met the same question as you are, and I get a comment in armv8 ARM G4.2.3

    quote "The term Typically configured is used in Figure G4-2 to indicate the expected software usage. However, stages of

    address translation used in AArch32 state can also be configured:

    • From an Exception level higher than the Exception level of the configuring PE mode shown in Figure G4-2,

    regardless of whether that Exception level is using AArch32 or is using AArch64, except that a Non-secure

    Exception level can never configure a stage of address translation that is used in Secure state.

    • From an Exception level that is using AArch64 and is higher than the level at which the translation stage is

    being used. For example, if Non-secure EL0 is the only Non-secure Exception level that is using AArch32,

    then the Non-secure PL1&0 stage of address translation is configured from Non-secure EL1, that is using

    AArch64"

    I guess that may help you.

  • 0

    hi Siles,

        I met the same problem as you r, and I get some Information from ARMv8 ARM G4.2.3.

        quotes "The term Typically configured is used in Figure G4-2 to indicate the expected software usage. However, stages of

    address translation used in AArch32 state can also be configured:

    • From an Exception level higher than the Exception level of the configuring PE mode shown in Figure G4-2,

    regardless of whether that Exception level is using AArch32 or is using AArch64, except that a Non-secure

    Exception level can never configure a stage of address translation that is used in Secure state.

    • From an Exception level that is using AArch64 and is higher than the level at which the translation stage is

    being used. For example, if Non-secure EL0 is the only Non-secure Exception level that is using AArch32,

    then the Non-secure PL1&0 stage of address translation is configured from Non-secure EL1, that is using

    AArch64."

        I think that may be the right answer.