These are per-core registers. In general ARM documents state if registers are shadowed. For example some of the registers like TTBR0 exist twice. Once for normal and a second time for secure world.
In contrast: The GIC contains global and per-core registers. But the GIC is a peripheral with respect to the core.
For the register types you mentioned, these are all per-core. That is, each core has an independent copy and can only see it's copy.
Thanks for this info. In the other word, A core cannot access another cores if no exception occur, also no need for accessing another core, (actually inter-acessing between cores depend on my software desgin), is that right understanding?
Cores cannot access the core internal registers of another core. Never. To exchange data between cores you need global "registers": Memory, periphperals like the GIC. But only by help of SW running on that core.