• State Accepted Answer
  • +1 person also asked this people also asked this
  • Locked Locked
  • Replies 7 replies
  • Subscribers 351 subscribers
  • Views 8750 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Information about ARM System control registers.

aketh

Hi all,

I noticed there are multiple system control registers in ARM.

The SCTLR_EL1 , SCTLR_EL2 and SCTLR_EL3.

I want to know, what do multiple such system controls registers represent??

I am particularly interested in the A bit of the system control register.

How does the A bit work when all these registers are involved?

For instance, When the A bit is enabled in say SCTLR_EL1 but not in SCTLR_EL2, what happen in case of an unaligned access? 

Do we encounter a segmentation fault?

if yes why?

Parents
  • +1 Arm Employee Badge in reply to aketh

    A higher EL can read a lower EL's registers but not the other way round.  For example, EL2 can see (and modify) the EL1 setting if it wants to but EL1 can neither see nor modify the EL2 setting.

    (EL2 needs to be able see and modify the EL1 to implement context switching of VMs.  An OS shouldn't care what setting the hypervisor is using, because it has not direct impact on the OS)

Reply
  • +1 Arm Employee Badge in reply to aketh

    A higher EL can read a lower EL's registers but not the other way round.  For example, EL2 can see (and modify) the EL1 setting if it wants to but EL1 can neither see nor modify the EL2 setting.

    (EL2 needs to be able see and modify the EL1 to implement context switching of VMs.  An OS shouldn't care what setting the hypervisor is using, because it has not direct impact on the OS)

Children
No data