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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
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  • Not Answered

    Calling None-Secure method directly from Secure world 0

    • TrustZone
    • Armv8-M
    • Block
    14504 views
    7 replies
    Latest over 7 years ago
    by Uma Ramalingam Arm Employee Badge
  • Answered

    GIC-400 controller virtual interrupt handling in VM and hypervisor +1

    • Cortex-A57
    • Generic Interrupt Controller
    • Cortex-A
    8323 views
    2 replies
    Latest over 7 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    efficient c programming 0

    • Cortex-R
    • Cortex-M
    • C
    5734 views
    4 replies
    Latest over 7 years ago
    by Wenchuan2018
  • Answered

    Using arm softcore in Kintex 7 board 0

    • Keil MDK
    • Cortex-M
    3840 views
    1 reply
    Latest over 7 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    Trustzone FIQ latency measurement When security extension is enabled +1

    • Armv7-A
    • Cortex-A
    • Cortex-A7
    • TrustZone
    6939 views
    3 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Suggested Answer

    Where can i find resources about creating program on cortex-m7 from scratch? 0

    • Cortex-M7
    • Cortex-M
    2856 views
    1 reply
    Latest over 7 years ago
    by Sebastian Floss
  • Suggested Answer

    Which ARMv8 register controls cache partitioning 0

    • Cache
    • Armv8-A
    6956 views
    1 reply
    Latest over 7 years ago
    by Christopher Tory Arm Employee Badge
  • Answered

    Is a DMB required between loading BASEPRI and storing BASEPRI_MAX? 0

    • Cortex-M7
    • Armv7-M
    • Cortex-M
    7968 views
    6 replies
    Latest over 7 years ago
    by Ramzyo
  • Not Answered

    Does Cortex R4x support SPI? 0

    • Cortex-R
    • Interface
    • Cortex-R4
    2290 views
    0 replies
    Started over 7 years ago
    by Anurag_Kumar
  • Answered

    Cortex-A7 Generic Timer Clock and Operation +1

    • Cortex-A
    • Cortex-A7
    10979 views
    4 replies
    Latest over 7 years ago
    by linda zhang
  • Answered

    What are the real benefits of implementing IDAU from the viewpoint of chip designers? 0

    • Address
    • ACE
    • AXI
    • Statement
    • TrustZone
    • Armv8-M
    • Secure Transactions
    • Memory
    8615 views
    1 reply
    Latest over 7 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    How to debug TF-M ns code on FVP_MPS2_AEMv8M? 0

    • Security
    • TrustZone
    • Armv8-M
    8942 views
    1 reply
    Latest over 7 years ago
    by Tao Lu
  • Answered

    DMB, DSB, ISB on Cortex M3,M4,M7 Single Core parts +1

    • Cortex-M7
    • Armv7-M
    • Cortex-M3
    • Cortex-M
    • Cortex-M4
    15069 views
    3 replies
    Latest over 7 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    Given an address, how to check its IDAU Security attribution information? 0

    • Architecture
    • Address
    • CHI
    • Security
    • TrustZone
    • Armv8-M
    13066 views
    6 replies
    Latest over 7 years ago
    by Tao Lu
  • Suggested Answer

    M0 Analog-Digital Conversion info needed 0

    • Cortex-M0
    • Cortex-M
    6718 views
    3 replies
    Latest over 7 years ago
    by Sebastian Floss
  • Answered

    How is a signed TF-M image loaded into memory with FVP_MPS2_AEMv8M? 0

    • Layout
    • Address
    • TrustZone
    • Armv8-M
    • Memory
    11989 views
    5 replies
    Latest over 7 years ago
    by Joseph Yiu Arm Employee Badge
  • Suggested Answer

    What happens to upper half of 32-bit data bus when reading 16-bit chip? 0

    • Cortex-M
    • Cortex-M4
    • AHB
    9007 views
    3 replies
    Latest over 7 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    TRFCR_EL1 register +1

    • CHI
    • Armv8
    4588 views
    1 reply
    Latest over 7 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    ARMv8 mmu problem +1

    • Armv8-A
    • Memory Management Unit (MMU)
    • Cortex-A
    27383 views
    16 replies
    Latest over 7 years ago
    by Ash Wilding Arm Employee Badge
  • Answered

    indirect branches in ARMv8 0

    • Cortex-A53
    • AArch64
    • Armv8-A
    • Cortex-A
    8428 views
    2 replies
    Latest over 7 years ago
    by Martin Weidmann Arm Employee Badge
<>
Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
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  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
  • Cortex-A7
  • Cortex-A8
  • Cortex-A9
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  • Cortex-M0
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  • Cortex-M7
  • Cortex-R
  • Interrupt
  • Linux
  • Memory
  • Memory Management Unit (MMU)
  • NEON
  • TrustZone