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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3592 Questions
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  • Not Answered

    BusFault on Power Reset 0

    • 5 (BusFault)
    • 3 (HardFault)
    2629 views
    1 reply
    Latest over 5 years ago
    by 42Bastian Schick
  • Answered

    const unsigned int iPage0CS[2] __at(0x07F8) = {0xFFFFFFFF,0x16400000}; +1

    3411 views
    1 reply
    Latest over 5 years ago
    by BJS
  • Not Answered

    Unexpected MPU fault 0

    • Cortex-M7
    • CMSIS
    3323 views
    0 replies
    Started over 5 years ago
    by Twoism
  • Not Answered

    A53 Erratum 820719 missing from official ARM errata document list 0

    • Cortex-A53
    16327 views
    0 replies
    Started over 5 years ago
    by ekta
  • Answered

    Forced Hardfault (INVPC) Exception Error +2

    • Cortex-M3
    • Cortex-M
    • Cortex-M4
    11553 views
    5 replies
    Latest over 5 years ago
    by Joseph Yiu Arm Employee Badge
  • Not Answered

    the width of AXI ID conflict 0

    19571 views
    1 reply
    Latest over 5 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Enable and disable MMU page table caching in L2 +1

    20324 views
    3 replies
    Latest over 5 years ago
    by XNoOp
  • Not Answered

    Debugger cannot execute cast and vectorization commands 0

    • Armv8-A
    • Debugger
    17807 views
    3 replies
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    How to use L2 cache as memory from ACP access on zynq Cortex A9 ? 0

    26685 views
    10 replies
    Latest over 5 years ago
    by XNoOp
  • Not Answered

    Pragma ignoring error when using arm-linux-androideabi-4.9 toolchain 0

    15954 views
    1 reply
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    VFMA instruction timings on ARM Cortex-M4 0

    1896 views
    0 replies
    Started over 5 years ago
    by EnricoTabanelli
  • Not Answered

    How to check whether the executing program uses cache memory for low latency? 0

    17722 views
    1 reply
    Latest over 5 years ago
    by XNoOp
  • Not Answered

    How does the memory regions are mapped in A72 cortex? 0

    18661 views
    2 replies
    Latest over 5 years ago
    by XNoOp
  • Not Answered

    L2 cache error injection and Prefetch Abort 0

    16670 views
    1 reply
    Latest over 5 years ago
    by XNoOp
  • Not Answered

    Penalty estimate of TLB miss or table walk in armv8 0

    17343 views
    2 replies
    Latest over 5 years ago
    by XNoOp
  • Suggested Answer

    STM32H745 dual-core debugging with IAR toolchain 0

    • Cortex-M7
    • stm32 h7
    • Cortex-M
    • Debugger
    • Cortex-M4
    4637 views
    1 reply
    Latest over 5 years ago
    by Andy Neil
  • Not Answered

    Seeking more information on SError on A53 core 0

    18862 views
    2 replies
    Latest over 5 years ago
    by KPK
  • Not Answered

    Why L1 cache associativity DOUBLED and index method CHANGED from the programmer's point of view? 0

    • Cache
    18342 views
    4 replies
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    IRQ Execution in nRF51 0

    • Cortex-M0
    3438 views
    1 reply
    Latest over 5 years ago
    by Andy Neil
  • Answered

    Question about PMU in detail 0

    17963 views
    3 replies
    Latest over 5 years ago
    by zilly
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