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Cortex-M3 Registers

Hello guys.

I am studying the Cortex-M3 technical reference manual.

I have some doubts:
- What is the function of each of the 13 general purpose 32-bit registers, R0 to R12?
- What does Link Register (LR) do?
- What is the function of the xPSR register?
- What does the DebugReturnAdress() register do?
- What is the function of CONTROL, FAULTMASK, BASEPRI, PRIMASK of register 5b10100?

Thank you in advance!

Top replies

42Bastian Schick over 5 years ago in reply to Fabiano Junqueira +1

This book is cheap and every penny worth if you work with cortex-m

0 Andy Neil over 5 years ago

Try this:

https://www.elsevier.com/books/the-definitive-guide-to-the-arm-cortex-m3/yiu/978-1-85617-963-8

Fabiano Junqueira said:
What is the function of each of the 13 general purpose 32-bit registers

The clue is in the name!
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0 Fabiano Junqueira over 5 years ago in reply to Andy Neil

Hi Andy, thank you very much for the reply.

I would like to know if it is really necessary to buy this document, and if I make the purchase and cannot find the answer I am looking for?

Thanks in advance!
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0 42Bastian Schick over 5 years ago in reply to Fabiano Junqueira

This book is cheap and every penny worth if you work with cortex-m
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0 Andy Neil over 5 years ago in reply to Fabiano Junqueira

Well, of course it's not necessary - but it will be extrmemely useful!

It will be money well spent.

It depends if you'd rather spend your time googling and studying the ARM documentation...
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0 John663 over 5 years ago

See here: https://www.egr.msu.edu/classes/ece331/mason/web_files/ARM_CortexM3.pdf/quickpayportal
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0 Fabiano Junqueira over 5 years ago

Thank you very much for the support, clarified many of my doubts.

In the memento I loaded a binary (firmware) in RAM via SWD and I would like to run it, however, I don't know how to do it. My question is not related to the SWD protocol and how to access the Cortex-M3 registers. My question is related to what steps should I follow to execute this binary that is in RAM.

Is there any step-by-step manipulation of the Cortex-M3 registers to execute this firmware present in RAM?

Thank you very much and I look forward to your reply.
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0 Andy Neil over 5 years ago in reply to Fabiano Junqueira

Please stick to 1 question per thread.

Perhaps you should study this: http://www2.keil.com/mdk5/learn

also: http://www.keil.com/support/man/docs/mdk_gs/

and: http://www.keil.com/support/man/docs/uv4/

and: http://www.keil.com/books/
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0 Fabiano Junqueira over 5 years ago in reply to Andy Neil

Thanks for the answer, but I don't know if my question was clear to you, because the links previously sent by you do not have the necessary content to solve my problem.

I need help to make an application located in RAM run using instructions sent via SWD. I know that for this I will need to manipulate the registers "PC" "MSP" "R0" and some others. My question is not related to the SWD protocol. I already do the manipulations of the protocol correctly, because I can read the application that is in RAM and I have access to the registers "PC", "MSP" and "R0" via SWD.

How should these registers ("PC", "MSP" and "R0") be handled for the application present in RAM to execute?

Thank you!
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0 Andy Neil over 5 years ago in reply to Fabiano Junqueira

That's a new question - start a new thread!
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0 Fabiano Junqueira over 5 years ago in reply to Andy Neil

Okay I started a new discussion. Follow the link: https://community.arm.com/developer/ip-products/processors/f/cortex-m-forum/46748/cortex-m3-registers
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