Arm Community
Arm Community
  • Site
  • User
  • Site
  • Search
  • User
Support forums
Support forums
Architectures and Processors forum
  • Jump...
  • Cancel
  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3594 Questions
Help a member

Have a question? If you can, please take a moment to also see if there is a question that you are able to answer.

  • Tags
  • RSS
  • More actions
  • Cancel
Other forums
  • AI forum

  • Architectures and Processors forum

  • Arm Development Platforms forum

  • Arm Development Studio forum

  • Arm Virtual Hardware forum

  • Automotive forum

  • Compilers and Libraries forum

  • Embedded and Microcontrollers forum

  • High Performance Computing (HPC) forum

  • Internet of Things (IoT) forum

  • Keil forum

  • Laptops and Desktops forum

  • Mobile, Graphics, and Gaming forum

  • Morello forum

  • Operating Systems forum

  • Servers and Cloud Computing forum

  • SoC Design and Simulation forum

  • SystemReady Forum

  • Answered

    Multi copy atomicity and usage of observers 0

    8932 views
    1 reply
    Latest over 11 years ago
    by Chris Shore
  • Answered

    Cortex-M3:Little endian 0

    • Cortex-M3
    • Cortex-M
    10767 views
    1 reply
    Latest over 11 years ago
    by Simon Craske Arm Employee Badge
  • Answered

    What is single-copy atomicity and how it is used in the software programming? 0

    11739 views
    1 reply
    Latest over 11 years ago
    by Chris Shore
  • Answered

    LDM to LTP Reason 0

    9330 views
    5 replies
    Latest over 11 years ago
    by techguyz
  • Answered

    What is the PMU counter resolution when the processor switches between 64-bit and 32-bit mode? 0

    • AArch64
    • Armv8
    • 64-bit
    • AArch32
    5520 views
    1 reply
    Latest over 11 years ago
    by Chris Shore
  • Answered

    Difference between co-processor registers and System registers 0

    • Armv7
    • Armv8
    4339 views
    1 reply
    Latest over 11 years ago
    by Chris Shore
  • Answered

    Code execution taking ages!! +1

    • Cortex-M
    3622 views
    1 reply
    Latest over 11 years ago
    by Kashif
  • Answered

    Using shareable attribute in MPU configuration of Cortex R4 +1

    • L1
    • AXI
    • Cache
    • Memory Protection Unit (MPU)
    • L2
    • Cortex-R4
    6586 views
    1 reply
    Latest over 11 years ago
    by Chris Shore
  • Answered

    What's the Cortex-A12 Main Bus Interface? 0

    • Cortex-A12
    • Cache coherency
    • ACE
    9531 views
    7 replies
    Latest over 11 years ago
    by Peter Harris Arm Employee Badge
  • Answered

    question about TrustZone's third party IP 0

    3344 views
    1 reply
    Latest over 11 years ago
    by Peter Harris Arm Employee Badge
  • Answered

    Organization of startup from internal flash of Cortex M3 0

    • Cortex-M3
    5327 views
    2 replies
    Latest over 11 years ago
    by Volker Kugler
  • Answered

    Flash programming in ASM for Cortex M4 0

    • Arm Assembly Language (ASM)
    • Cortex-M4
    8931 views
    4 replies
    Latest over 11 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    Design Start ARM Cortex-M0 0

    • AMBA
    • Cortex-M
    • Interface
    57636 views
    33 replies
    Latest over 11 years ago
    by vivek
  • Not Answered

    How and Where do I change Endianness in Cortex-A9? 0

    • Cortex-A
    13726 views
    2 replies
    Latest over 11 years ago
    by Senthil Kumar Rajagopal
  • Not Answered

    Question : The Definitive Guide to the ARM Cortex-M3 0

    • Cortex-M3
    • Cortex-M
    24177 views
    33 replies
    Latest over 11 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    cortex-m3 pipeline stages, branch prediction 0

    • Cortex-M
    19003 views
    2 replies
    Latest over 11 years ago
    by Alexander Brunner
  • Answered

    How to calculate the CPI for ARM Cortex-R4 0

    • Cortex-R
    10151 views
    3 replies
    Latest over 11 years ago
    by Peter Harris Arm Employee Badge
  • Answered

    CPUACTLR_EL1 and S3_1_C15_C2_0 in Cortex-A57 TRM 0

    • Cortex-A
    11702 views
    4 replies
    Latest over 11 years ago
    by chinatiger
  • Answered

    Using ARM1176JZF-S Kit (DS-5 tools), I need to control stepper motor based on the output of ultrasonic sensor (which detects objects). +1

    • Arm Development Studio
    • arm1176jzf-s
    • Arm11
    8210 views
    7 replies
    Latest over 11 years ago
    by albert dane
  • Answered

    Does ARMv8 SOC support cache lockdown? 0

    • Cortex-A
    18966 views
    12 replies
    Latest over 11 years ago
    by chinatiger
<>
Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
  • Armv8-M
  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
  • Cortex-A7
  • Cortex-A8
  • Cortex-A9
  • Cortex-M
  • Cortex-M0
  • Cortex-M3
  • Cortex-M4
  • Cortex-M7
  • Cortex-R
  • Interrupt
  • Linux
  • Memory
  • Memory Management Unit (MMU)
  • NEON
  • TrustZone