Which instruction format does Cortex-R support,encoding A1 orA2?

I must admit I've never noticed those T1, T2 etc before, but I believe the answer is you shouldn't have to worry about that if you have a Cortex-R as they support the ARMv7 architecture.

Those T1, T2, T3 encodings are where the same instruction has a number of different encodings depending normally on what registers can be used, the compiler or assembler will automatically choose the correct one to use. The ARMv7' after the encoding type is the important bit as some forms were not supported in earlier versions of the architecture. All the Cortex-R processors support ARMv7 which includes all the Thumb-2 instructions and I think they support all the ARM 32 bit instructions too except there may be variations in the floating point support. The same is true of the A1 A2 encodings though there's normally only the one form for a 32 bit ARM instruction

Encoding A1 and A2 have different range of immediate constants.And,I want to know the rang of operand 2 for MOV for Cortex.It's useful for program,isn't it?

Hi,

> Encoding A1 and A2 have different range of immediate constants.And,I want to know

> the rang of operand 2 for MOV for Cortex.It's useful for program,isn't it?

Note that for this case there is an applicable syntax for A1 and A2.

If you write:

    MOV Rd, #<const>

... the A1 format would be used, and <const> must not exceed the 12-bit range. If <const> is too large, the compiler/assembler would generate an error and advise you to use the MOVW syntax.

If you write:

    MOVW Rd, #<const>

... the A2 format would be ued, and the range for <const> can be 16-bit.

Xingguang

It should assemble a MOV with the 16-bit constant as a MOVW if the cpu option specifies an ARMv7 device, have you done that?

You can see the MOVW encoding only came in with ARMv6T2, so one could only use 8 bit shifted constants before then.

MOV and MOVN  are good for loading common constants where most of the bits are zero or one. They load an 8-bit constant or its negated value and rotate the 32 bit register, so MOV can for instance load 0x00520000.
MOVW is especially useful paired with MOVT to load a 32 bit address.

Now I just talk about ARMv7 Architecture.

The picture above shows that ARMv7 Architecture support both encoding A1 and A2.

So I think MOV should be with 12bit constant.

But in my project I did assemble a MOV with the 16-bit constant,and CCS didn't shows any errors.Why?

And does one project support encoding A1 and A2 at the same time?

I believe it is at the discretion of the assembler whether it will use the A2 encoding to encode a MOV instruction with a 16-bit constant (assuming that you are using an ARMv7 processor as all these support both coding).

In general, assemblers will do this wherever possible. Note that the A2 encoding cannot set the flags (the S is not an available option with MOVW) so if you wrote MOVS with a 16-bit constant, it would not be able to use the A2 coding and would most likely generate an assembly error.

Chris

Do you mean that the instruction I wrote(MOV or MOVW) is the only one reson for assembler to use A1 or A1 encoding?

But the picture below shows that MOV is permitted by all encodings.

Yes, the mnemonic you write in assembler (MOV or MOVW) is only one part of the choice of the encoding which the assembler will emit.

If you write MOV, the assembler is free to choose from all available encodings (provided the registers used, the choice of flag-setting and the length of the constant fit options for the encoding).

So, if you write MOV r0, #8, the assembler can choose from all available encodings for the instruction except T1 (because T1 always sets the flags).

If you write MOVS r0, #8, it could choose from T1, T2 or A1. It will choose T1 because it's the shortest. For other values of the constant, it might prefer T2 or A1.

If you write MOV with a 16-bit constant which cannot be encoded in the 12-bit format, the assembler will use encoding T3 or A2. The only difference between them is that A2 cannot be used when the destination register is PC, and T3 cannot be used when the destination register is PC or SP.

However, if you write MOVW, it will be restricted to use T3 or A2. So, if you really must have one of those two, write MOVW.

Hope that makes sense!

Chris

I think I should point out that A1 format is not a 12-bit constant. It is an 8 bit constant rotated around by a power of 0,2,4,..30 so that for instance

0x00057000 can be encoded

0x345 cannot be encoded

whereas for MOVW ( which will be used automatically if necessray)

0x00057000 cannot be encoded

0x345 can be encoded

You're absolutely right - thanks for pointing that out. 12-bit AREM constants are strange beasts!

They're very useful though. The Aarch64 also has a lot of strange but very useful constant encodings, a characteristic of the ISA that has thankfully been kept whatever about all the other simplifications.

Thank you for your help.

Thank you for your help.