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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3581 Questions
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  • Answered

    Caches EL3 and EL1 on A53 Clusters +1

    3702 views
    5 replies
    Latest over 3 years ago
    by jzbiciak
  • Not Answered

    DS-5: bare bones assembly project that can be debugged? 0

    • Arm Assembly Language (ASM)
    • DS-5 Community Edition
    1257 views
    1 reply
    Latest over 3 years ago
    by WestfW
  • Answered

    Find out instruction latency and throughput for NEON and SVE instructions 0

    • optimization
    • NEON
    • SVE
    • Neoverse N1
    3264 views
    2 replies
    Latest over 3 years ago
    by _l_m_m_y_
  • Not Answered

    Memory attribute configuration in SMMU-v3 0

    • SMMUv3
    3112 views
    4 replies
    Latest over 3 years ago
    by gchww
  • Not Answered

    LPC313x / LPC314x CDL package 0

    963 views
    0 replies
    Started over 3 years ago
    by derek57
  • Suggested Answer

    What is the response if master issues normal transaction to secure slave 0

    1165 views
    1 reply
    Latest over 3 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Why only first half of register bank is accessible in VFP's S0-31 register bank? 0

    • Armv7-M
    1177 views
    0 replies
    Started over 3 years ago
    by Paul B
  • Suggested Answer

    Defining power on execution state of LS1027A dual ARM Cortex A72 core SoC 0

    1275 views
    1 reply
    Latest over 3 years ago
    by vstehle Arm Employee Badge
  • Answered

    How could I read cache internal memory in Cortex-A72 0

    • Cache Management
    • Debugging
    1553 views
    1 reply
    Latest over 3 years ago
    by vstehle Arm Employee Badge
  • Answered

    Provision to get out of BKPT instruction +1

    14123 views
    10 replies
    Latest over 3 years ago
    by garkbeda43
  • Answered

    In CM7, how NVIC distinguishes pulse and level interrupts? 0

    • Interrupt Handling
    • Cortex-M
    1980 views
    1 reply
    Latest over 3 years ago
    by Mahmood Yakub Arm Employee Badge
  • Answered

    How to connect peripherals in CoertexR5 processor? And also how many possible ways of connecting them? +1

    • Cortex-R5
    • Armv7-R
    1555 views
    2 replies
    Latest over 3 years ago
    by Buvanesh
  • Not Answered

    Memory attribute configuration in SMMU-v3 0

    1192 views
    0 replies
    Started over 3 years ago
    by gchww
  • Not Answered

    ShenZhen Hao Qi Core Technology Analysis: What are the techniques for chip decryption? 0

    1757 views
    1 reply
    Latest over 3 years ago
    by vinniesenger
  • Answered

    In ARM Cortex R5 TRM, Number of MPU region is stated as 12 or 16 in MPU chapter and 8 and 12 in chapter 2. Which one is correct? 0

    • Cortex-R5
    • Armv7-R
    1670 views
    2 replies
    Latest over 3 years ago
    by Buvanesh
  • Suggested Answer

    About the difference between the terms l3_cache and ll_cache 0

    • Cache Controllers
    • Cache Architecture
    2063 views
    1 reply
    Latest over 3 years ago
    by Eugene Choi Arm Employee Badge
  • Answered

    Can Cortex A8 NEON optimized code work on Cortex A5 NEON? 0

    2583 views
    6 replies
    Latest over 3 years ago
    by zhongl
  • Answered

    EL1 Interrupt handler in C for Cortex R52 0

    3284 views
    6 replies
    Latest over 3 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    On Cortex-M7, can speculative access bring accessed data to D cache? 0

    • Cortex-M7
    • Cache Management
    5438 views
    6 replies
    Latest over 3 years ago
    by Zenon (Zhilong) Xiu Arm Employee Badge
  • Answered

    Does TZASC still work in ARMv9 when RME is implemented? 0

    2212 views
    2 replies
    Latest over 3 years ago
    by Zenon (Zhilong) Xiu Arm Employee Badge
<>
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