AXI4 narrower transactions for AWADDR


Below is the connection.

My IP based on AXI-4 lite <-> 64bit -> Interconnect <-AXI4->  64bit ARM A53

Upper 32bit data (ex addr: 0x1004) got cleared once I write lower 32bit data (ex addr: 0x1000) from ARM core to my IP registers and vice versa.

64bit  (ex addr: 0x1000-0x1007) write and read seems to be working. So just looking into signals and need some insights.

Now my question is that when I perform narrower transactions on AXI4 from ARM to my IP through aforementioned connection how should be AWADDR & WSTRB signals for address 0x1004 upper 32bit txn ?

i) AWADDR = 0x1004 & WSTRB = 0xF0 ??

ii) AWADDR = 0x1000 & WSTRB = 0xF0 ??

I should set AWADDR as 0x1000 or 0x1004 in this case as per spec & standards ? because my IP expects 64bit boundary address, may be thats why lower 32bit data cleared when I write upper 32bit !?

PS: 0x1000 is 64bit boundary IP reg based on AXI-4 lite

  • AXI4-lite doesn't have any AWSIZE signal as all transfers are to the full width of the data bus, so if you only want to write 32-bits of data it would be the WSTRB bits that define the valid byte lanes.

    From a protocol perspective there wouldn't then be any difference in your two example transfers as WSTRB indicates in both that it is the upper half of the data bus containing the valid data. AWADDR can be either 0x1000 or 0x1004 as all the AWADDR value does is restrict the possible byte lanes that could be used. 0x1000 allows any of the 8 byte lanes to be used, 0x1004 allows only the upper 4 byte lanes.

    If your AXI4-lite IP design requires AWADDR to only ever be 64-bit aligned, that could be the reason why you are seeing failures, but it sounds more likely that your IP is not looking at WSTRB to determine which byte lanes to consider as valid.