Hi Arm team,
We are experiencing a high CPU load (95%)in the System which is based on the “CYT4BFX” microcontroller(based on M7) whereas the other system which is based on CYT2B9X(based on M4) has significantly less CPU load of 25% even though it's running at 80Mhz clock speed where are CYT4BFX is running at a higher frequency of 160Mhz.
Our software is based on Autosar architecture (OSEK OS),We used the same BSW SIP and same application software and the BSW configuration is almost the same.
We are using the same compiler and same compiler options in both projects. We did not enable cache (Data or instruction cache) or ITCM/DTCM(Tightly-Coupled Memory).
Could you please suggest possible ways to reduce CPU Load in the CYT4BFX system?.
I tried to enable the Data cache and instruction cache using the following M7 library functions,(I did not choose what part of memory is cacheable and not enabled MPU) this resulted in a memory exception.I did not find any M7 library functions to choose what part of memory can be cachable.As I am new to cache functionality usage,could you please suggest what aspects of software can be moved to the Data cache or instruction cache?.
SCB_InvalidateICache();SCB_EnableICache();SCB_EnableDCache();
Are there any library functions to choose what part of memory can be cachable ?.
What part of embedded software can be chosen to run in TCM memory that helps to reduce the load?Are there any library functions to enable /configure TCM functionality?.
Many thanks.
Regards,
Bhaskar