Does Cortex-A55 could work on AARCH32 state at the EL1

Dear everyone:

I baremetal boot the Cortex-A55,want it to work on AARCH32 state at the EL1,but always into the exception.

I refer to the book which named DAI0527A_baremetal_boot_code_for_ARMv8_A_processors .

// Initialize the SCTLR_EL1 register before entering EL1.
MSR SCTLR_EL1, XZR
MRS X0, HCR_EL2
BIC X0, X0, #(1<<31) // RW=0 EL1 Execution state is AArch32.
MSR HCR_EL2, X0

MOV X0, #0b10011 // DAIF=0000
MSR SPSR_EL2, X0 // M[4:0]=10011 EL1 is SVC mode must match HCR_EL2.RW.
// Determine EL1 Execution state.
ADR X0, el1_entry // el1_entry points to the first instruction of SVC
MSR ELR_EL2, X0 // mode code.
ERET
el1_entry:
// EL1 code here.