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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3590 Questions
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  • Answered

    What is the PMU counter resolution when the processor switches between 64-bit and 32-bit mode? 0

    • AArch64
    • Armv8
    • 64-bit
    • AArch32
    5511 views
    1 reply
    Latest over 11 years ago
    by Chris Shore
  • Answered

    Difference between co-processor registers and System registers 0

    • Armv7
    • Armv8
    4312 views
    1 reply
    Latest over 11 years ago
    by Chris Shore
  • Answered

    Code execution taking ages!! +1

    • Cortex-M
    3615 views
    1 reply
    Latest over 11 years ago
    by Kashif
  • Answered

    Using shareable attribute in MPU configuration of Cortex R4 +1

    • L1
    • AXI
    • Cache
    • Memory Protection Unit (MPU)
    • L2
    • Cortex-R4
    6567 views
    1 reply
    Latest over 11 years ago
    by Chris Shore
  • Answered

    What's the Cortex-A12 Main Bus Interface? 0

    • Cortex-A12
    • Cache coherency
    • ACE
    9482 views
    7 replies
    Latest over 11 years ago
    by Peter Harris Arm Employee Badge
  • Answered

    question about TrustZone's third party IP 0

    3322 views
    1 reply
    Latest over 11 years ago
    by Peter Harris Arm Employee Badge
  • Answered

    Organization of startup from internal flash of Cortex M3 0

    • Cortex-M3
    5289 views
    2 replies
    Latest over 11 years ago
    by Volker Kugler
  • Answered

    Flash programming in ASM for Cortex M4 0

    • Arm Assembly Language (ASM)
    • Cortex-M4
    8890 views
    4 replies
    Latest over 11 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    Design Start ARM Cortex-M0 0

    • AMBA
    • Cortex-M
    • Interface
    57480 views
    33 replies
    Latest over 11 years ago
    by vivek
  • Not Answered

    How and Where do I change Endianness in Cortex-A9? 0

    • Cortex-A
    13693 views
    2 replies
    Latest over 11 years ago
    by Senthil Kumar Rajagopal
  • Not Answered

    Question : The Definitive Guide to the ARM Cortex-M3 0

    • Cortex-M3
    • Cortex-M
    24027 views
    33 replies
    Latest over 11 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    cortex-m3 pipeline stages, branch prediction 0

    • Cortex-M
    18930 views
    2 replies
    Latest over 11 years ago
    by Alexander Brunner
  • Answered

    How to calculate the CPI for ARM Cortex-R4 0

    • Cortex-R
    10116 views
    3 replies
    Latest over 11 years ago
    by Peter Harris Arm Employee Badge
  • Answered

    CPUACTLR_EL1 and S3_1_C15_C2_0 in Cortex-A57 TRM 0

    • Cortex-A
    11657 views
    4 replies
    Latest over 11 years ago
    by chinatiger
  • Answered

    Using ARM1176JZF-S Kit (DS-5 tools), I need to control stepper motor based on the output of ultrasonic sensor (which detects objects). +1

    • Arm Development Studio
    • arm1176jzf-s
    • Arm11
    8133 views
    7 replies
    Latest over 11 years ago
    by albert dane
  • Answered

    Does ARMv8 SOC support cache lockdown? 0

    • Cortex-A
    18911 views
    12 replies
    Latest over 11 years ago
    by chinatiger
  • Answered

    ARM7 Programming question! +1

    • Arm7
    • Arm Assembly Language (ASM)
    9022 views
    7 replies
    Latest over 11 years ago
    by Velagala J R N D V Reddy
  • Answered

    RTOS ARM7 BOARD +1

    • Arm7
    4073 views
    2 replies
    Latest over 11 years ago
    by oska874
  • Answered

    What is the difference between PoC and PoU for Cortex-A7 MPCore? 0

    12426 views
    2 replies
    Latest over 11 years ago
    by chinatiger
  • Answered

    LPC2368 Watchdog Timer 0

    • APB
    • ACE
    • Cortex-M
    19092 views
    3 replies
    Latest over 11 years ago
    by Alban Rampon
<>
Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
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  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
  • Cortex-A7
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  • Cortex-M7
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  • Interrupt
  • Linux
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  • Memory Management Unit (MMU)
  • NEON
  • TrustZone