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Cortex A7 - Boot from SPI NOR vs Execution In Place (XIP)

ENRICO

Hi folks,

I've been working for years with ARM -M processors and I'm facing -A processors for the first time.

I fell in love with Allwinner's V3S processor which is v7-A type.

The datasheet says that the processor is able to boot from an external SPI NOR memory.

The datasheet doesn't say anything about Execution In Place (XIP)

Question

Can I assume that the processor is able to execute code (XIP) directly from the SPI NOR external memory?

Thanks in advance,

Enrico Migliore

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    I doubt you can execute anything in SPI Flash. First it is serial thus very slow, secondly SF are usually bytes page sized with erasable sizes even in Kbytes, eg. mine which is NOR is page size 64 bytes and erase size 64 Kbytes so image how do you want to eg. modify a variable there. to modify a variable that is eg. 4 bytes and you will have to erase 64K. Another thing is with instructions executed from inside flash with .data. .bss sections being in the memory (static or dynamic). 

    I know some architectures have SPI flashes memory mapped so it is easier to use them.

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    I doubt you can execute anything in SPI Flash. First it is serial thus very slow, secondly SF are usually bytes page sized with erasable sizes even in Kbytes, eg. mine which is NOR is page size 64 bytes and erase size 64 Kbytes so image how do you want to eg. modify a variable there. to modify a variable that is eg. 4 bytes and you will have to erase 64K. Another thing is with instructions executed from inside flash with .data. .bss sections being in the memory (static or dynamic). 

    I know some architectures have SPI flashes memory mapped so it is easier to use them.

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