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thumb 2 instruction set

sana srikar
The thumb 2 instruction contains both the instruction sets( best of both worlds) ARM and THUMB.
 
So my question is how does processor come to know that the fetched one  is 16 bit size instruction or 32bit size instruction

why this doubt:

in joesph yiu in pgno 60 second paragah fourth line it is given as

"In fact, Cortex-M processors does not support 32-bit instructions at all" is this true? or am I  getting this wrong ? 

and one more extension to my doubt is while fetching instructions in how many bits is fetching done ........

are 16 bits fetched at once or 32 bits or 8 bits?

i am confused with this thumb2 instruction set ....................and what is prefetch?  

thanks for the answers in advance 

Parents
  • 0 in reply to cray
    cray do you mean this ?
    cortex M does not support ARM instruction which is 32 bit but instead it supports thumb-2 (mix of both 16 and32 bit) instructions?

    if i get clarity in this then my question will be solved.
    and thanks for telling me to read the manual pdf it is helping me
Reply
  • 0 in reply to cray
    cray do you mean this ?
    cortex M does not support ARM instruction which is 32 bit but instead it supports thumb-2 (mix of both 16 and32 bit) instructions?

    if i get clarity in this then my question will be solved.
    and thanks for telling me to read the manual pdf it is helping me
Children
  • 0 in reply to sana srikar
    yes, your understanding is correct.
  • 0 in reply to cray
    cary i was learning stm32f407VG micro controller and there was something called prefetch i know the meaning of what it is but could you pls provide some more info on that
  • 0 in reply to sana srikar
    The purpose of the Prefetch Unit (PFU) is to:
    • Fetch instructions in advance and forward PC relative branch instructions.
    Fetches are speculative in the case of conditional branches
    • Detect Thumb-2 instructions and present these as a single instruction word.
    • Perform vector loads.
    The PFU fetches instructions from the memory system that can supply one word each
    cycle. The PFU buffers up to three word fetches in its FIFO, which means that it can
    buffer up to three Thumb-2 instructions or six Thumb instructions.
    The majority of branches that are generated as the ALU addition of PC plus immediate
    are generated no later than the decode phase of the branch opcode. In the case of
    conditionally executed branches, the address is speculatively presented (consuming a
    fetch slot on the bus), and the forwarded result determines if the branch path flushes the
    fetch queue or is preserved.
    Short subroutine returns are optimized to take advantage of the forwarding behavior in
    the case of BX LR.
  • 0 in reply to cray

    could you pls provide me with some useful links on this topic cray

  • 0 in reply to sana srikar
    search DDI0337E_cortex_m3_r1p1_trm.pdf
    arm_cortexm3_processor_trm_100165_0201_00_en.pdf