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How cortex-M4 handles data hazard situations in the pipeline?

Hello to all,

Since I am working on ARM Cortex-M4, I would like to know about the handling of the hazard situations (especially the RAW, WAR and WAW hazard situations) in the pipeline.

Is the processor also use the method of "Forwarding" in order to handle such situation or is there some other way of handling?

Thanking you, 

Kind Regards, 

Himanshu 

Parents
  • RAW, WAR and WAW are generally hazards in the memory interface & memory systems. The AHB interface in Cortex-M3/M4 is in order (AHB does not have support of multiple outstanding transfers) and the write buffer is single entry, which mean all accesses are completed in the same order as they appears in the program. As a result there is no data hazard in those memory access sequences you mentioned.

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  • RAW, WAR and WAW are generally hazards in the memory interface & memory systems. The AHB interface in Cortex-M3/M4 is in order (AHB does not have support of multiple outstanding transfers) and the write buffer is single entry, which mean all accesses are completed in the same order as they appears in the program. As a result there is no data hazard in those memory access sequences you mentioned.

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