We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.
Hello to all,
Since I am working on ARM Cortex-M4, I would like to know about the handling of the hazard situations (especially the RAW, WAR and WAW hazard situations) in the pipeline.
Is the processor also use the method of "Forwarding" in order to handle such situation or is there some other way of handling?
Thanking you,
Kind Regards,
Himanshu
RAW, WAR and WAW are generally hazards in the memory interface & memory systems. The AHB interface in Cortex-M3/M4 is in order (AHB does not have support of multiple outstanding transfers) and the write buffer is single entry, which mean all accesses are completed in the same order as they appears in the program. As a result there is no data hazard in those memory access sequences you mentioned.
Dear Mr. Yiu,
Thank you very much for such a detailed information. But for some cases something unknowing things are going on. examples have been provided below:
Example 1 :
--------------------------------------------------------------------------------------------------------------
Instruction Sequence Current Consumption
Program-1
SBC R1,R2,R3
SBC R4,R1,R6 2.9424 mAmps
SBC R5,R4,R7
----------------------------------------------------------------------------------------------------------------
Program-2
SBC R4,R8,R6 2.8168 mAmps
SBC R9,R2,R11
-------------------------------------------------------------------------------------------------------------------
Example 2 :
ORN R1,R2,R3
ORN R4,R1,R6 2.8805 mAmps
ORN R5,R4,R7
ORN R4,R8,R6 2.8004 mAmps
ORN R9,R2,R11
Except for this two instruction sequence, rest all the Arithmetic and Logical instructions don't show any changes in current consumption for such instruction sequence. Also, we have also make sure that the Hamming weight of the operands should be same in both the cases.
But why these two instructions show such behavior?