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"CPSIE I"on an ARMv7A not changing the I bit in the CPSR register in USR mode - why?

I'm using a CortexA8 and I can't seem to enable interrupts...! 

I'm using a "CPSIE I" instruction, I can see that the compiler (GCC) is not optimizing my code out... I have to manually stop the program with a debugger and update the I bit myself before I can see an interrupt fire..!? 

Why? Any help would be much appreciated!

Cheers!